Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
7.2
Recommended Clock and Control Signal Transition
1
Digital Media System-on-Chip (DMSoC)
............
Behavior
...........................................
1.1
Features
.............................................
7.3
Power Supplies
....................................
1.2
Description
...........................................
7.4
External Clock Input From DEV_MXI/DEV_CLKIN
1.3
Functional Block Diagram
...........................
and AUX_MXI/AUX_CLKIN Pins
..................
2
Revision History
........................................
7.5
Clock PLLs
........................................
3
Device Overview
........................................
7.6
Enhanced Direct Memory Access (EDMA3)
3.1
Device Characteristics
...............................
Controller
..........................................
3.2
Device Compatibility
................................
7.7
Reset
..............................................
3.3
ARM Subsystem
....................................
7.8
Interrupts
..........................................
3.4
DSP Subsystem
....................................
7.9
External Memory Interface (EMIF)
................
3.5
Memory Map Summary
............................
7.10
DDR2 Memory Controller
.........................
3.6
Pin Assignments
....................................
7.11
Video Port Interface (VPIF)
.......................
3.7
Terminal Functions
.................................
7.12
Transport Stream Interface (TSIF)
................
3.8
Device Support
.....................................
7.13
Clock Recovery Generator (CRGEN)
.............
3.9
Documentation Support
............................
7.14
Video Data Conversion Engine (VDCE)
..........
3.10
Community Resources
.............................
7.15
Peripheral Component Interconnect (PCI)
........
4
Device Configurations
................................
7.16
Ethernet MAC (EMAC)
............................
4.1
System Module Registers
..........................
7.17
Management Data Input/Output (MDIO)
..........
4.2
Power Considerations
..............................
7.18
Host-Port Interface (HPI) Peripheral
..............
4.3
Clock Considerations
...............................
7.19
USB 2.0 [see Note]
...............................
4.4
Boot Sequence
.....................................
7.20
ATA Controller
.....................................
4.5
Configurations At Reset
............................
7.21
VLYNQ
............................................
4.6
Configurations After Reset
........................
7.22
Multichannel Audio Serial Port (McASP0/1)
Peripherals
Peripherals
........................................
4.7
Multiplexed Pin Configurations
....................
7.23
Serial Peripheral Interface (SPI)
..................
4.8
Debugging Considerations
........................
7.24
Universal Asynchronouse Receiver/Transmitter
5
System Interconnect
................................
(UART)
............................................
6
Device Operating Conditions
......................
7.25
Inter-Integrated Circuit (I2C)
......................
6.1
Absolute Maximum Ratings Over Operating Case
7.26
Pulse Width Modulator (PWM)
....................
Temperature Range (Unless Otherwise Noted)
..
7.27
Timers
.............................................
6.2
Recommended Operating Conditions
.............
7.28
General-Purpose Input/Output (GPIO)
............
6.3
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating
Ranges of Supply Voltage and Operating
7.29
IEEE 1149.1 JTAG
................................
Temperature (Unless Otherwise Noted)
..........
8
Mechanical Packaging and Orderable
7
Peripheral Information and Electrical
Information
............................................
Specifications
.........................................
8.1
Thermal Data for CUT
............................
7.1
Parameter Information
............................
8.2
Packaging Information
............................
6
Contents
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