Texas Instruments CC2650DK 사용자 설명서
uDMA controller
Control / Status
CTRL
ALTCTRL
CFG
STATUS
Control / Status
SETBURST
CLEARBURST
SOFTREQ
WAITONREQ
Control / Status
STECHANNELEN
CLEARCHANNELEN
CLEARREQMASK
SETREQMASK
Control / Status
SETCHNLPRIORITY
CLEARCHNLPRIORITY
CLEARCHNLPRIALT
SETCHNLPRIALT
Control / Status
DONEMASK
REQDONE
ERROR
System Memory
Transfer buffers used by
uDMA
Nested vector
interrupt controller
NVIC
CPU
UDMACHx burst req
Done
CPUIRQ
Event fabric
Peripheral N
Registers
UDMACHx single req
Re
q
q
u
e
st
e
v
e
n
t
In
te
rr
u
p
t
Active
Functional Description
Figure 12-1.
μDMA Block Diagram
12.3 Functional Description
The
μDMA controller is a flexible and highly configurable DMA controller designed to work efficiently with
the microcontroller Cortex-M3 processor core. The controller supports multiple data sizes and address
increment schemes, multiple levels of priority among DMA channels, and several transfer modes to allow
for sophisticated programmed data transfers.
increment schemes, multiple levels of priority among DMA channels, and several transfer modes to allow
for sophisticated programmed data transfers.
Each supported peripheral function has a dedicated channel on the
μDMA controller that can be
configured independently. The
μDMA controller implements a configuration method using channel control
structures maintained in system memory by the processor. While simple transfer modes are supported, it
is also possible to build up sophisticated task lists in memory that allow the
is also possible to build up sophisticated task lists in memory that allow the
μDMA controller to perform
arbitrary-sized transfers to and from arbitrary locations as part of a single transfer request. The
μDMA
controller also supports the use of ping-pong buffering to accommodate constant streaming of data to or
from a peripheral.
from a peripheral.
Each channel also has a configurable arbitration size. The arbitration size is the number of items that are
transferred in a burst before the
transferred in a burst before the
μDMA controller requests channel priority. Using the arbitration size, it is
possible to control exactly how many items are transferred to or from a peripheral every time it makes a
μDMA service request.
μDMA service request.
12.3.1 Channel Assignments
lists
μDMA channel assignments to peripherals.
1037
SWCU117A – February 2015 – Revised March 2015
Micro Direct Memory Access (µDMA)
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