Texas Instruments CC2650DK 사용자 설명서
Event
fabric
CH2_CLEAR
CH1
CH0
CLEAR
CLEAR
CAPTURE
CH2
CLEAR
CH0_EVENT
CH1_EVENT
CH2_EVENT
Registers
I/
O
b
o
rd
e
r
Programable event
DELAY
counter
DELAY
counter
DELAY
counter
I/
O
b
o
rd
e
r
AON RTC Module
Main counter
rtc_cnt[69:0]
rtc_cnt[53:22]
32 kHz
DIV 2
rtc_cnt[53:22]
rtc_cnt[53:22]
rtc_upd (16 kHz)
32 kHz
32 kHz
32 kHz
subsecinc
AUX
Functional Specifications
Figure 14-1. AON RTC Channels
14.2.4 Events
A programmable combination of the three delayed events can be combined into a seventh delayed event.
All events are fed to the AON event fabric, where they are available, for example, as wake-up events for
the MCU or AUX domains.
All events are fed to the AON event fabric, where they are available, for example, as wake-up events for
the MCU or AUX domains.
The three channels can individually generate an event. Each of these three events can generate a
corresponding event by delaying the channel event by a programmable amount of clocks, using a delay
counter. The delay counters use the uncompensated 32-kHz clock; thus, the delay time will vary with this
clock. This process can generate precise events in the future, even when, for example, the MCU must be
woken up following an event — a process that takes an indeterministic, yet bounded, amount of time.
corresponding event by delaying the channel event by a programmable amount of clocks, using a delay
counter. The delay counters use the uncompensated 32-kHz clock; thus, the delay time will vary with this
clock. This process can generate precise events in the future, even when, for example, the MCU must be
woken up following an event — a process that takes an indeterministic, yet bounded, amount of time.
NOTE:
Disabling a channel does not clear any pending events from that channel. The only way to
clear an event is by asserting the external clear signal, or by writing 1 to the corresponding
CHx bit in [AON_RTC:EVFLAGS].
CHx bit in [AON_RTC:EVFLAGS].
14.3 RTC Registers
The RTC registers are placed in the AON domain and are clocked using 32-kHz LF clock. All configuration
and status registers are preserved in all power modes except for SHUTDOWN. The MCU domain contains
an interface to the AON RTC registers to ensure fast access with minimum latency on the system bus.
Due to synchronization between the MCU interface and the AON domain, there is a delay in the system
that software must take into account.
and status registers are preserved in all power modes except for SHUTDOWN. The MCU domain contains
an interface to the AON RTC registers to ensure fast access with minimum latency on the system bus.
Due to synchronization between the MCU interface and the AON domain, there is a delay in the system
that software must take into account.
14.3.1 Register Access
A write access is delayed with one or two 32-kHz LF clock periods. The system bus is not affected by this
delay, so the MCU completes the bus transactions before the actual AON RTC register is written in the
AON RTC. This process enables the application to write several registers consecutively, without any extra
delay due to synchronization.
delay, so the MCU completes the bus transactions before the actual AON RTC register is written in the
AON RTC. This process enables the application to write several registers consecutively, without any extra
delay due to synchronization.
Due to synchronization, a read access will always read a value that is two to three system clocks (48
MHz) delayed. In this case, the system bus is not halted.
MHz) delayed. In this case, the system bus is not halted.
1126
Real-Time Clock
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated