Texas Instruments CC2650DK 사용자 설명서
Watchdog Timer Registers
15.4.1.7 TEST Register (Offset = 418h) [reset = X]
TEST is shown in
and described in
.
Test Mode
Figure 15-8. TEST Register
31
30
29
28
27
26
25
24
RESERVED
R-X
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
RESERVED
STALL
R-X
R/W-X
7
6
5
4
3
2
1
0
RESERVED
TEST_EN
R-X
R/W-X
Table 15-8. TEST Register Field Descriptions
Bit
Field
Type
Reset
Description
31-9
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
8
STALL
R/W
X
WDT Stall Enable 0: The WDT timer continues counting if the CPU
is stopped with a debugger. 1: If the CPU is stopped with a
debugger, the WDT stops counting. Once the CPU is restarted, the
WDT resumes counting.
is stopped with a debugger. 1: If the CPU is stopped with a
debugger, the WDT stops counting. Once the CPU is restarted, the
WDT resumes counting.
0h = Disable STALL
1h = Enable STALL
7-1
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
0
TEST_EN
R/W
X
The test enable bit 0: Enable external reset 1: Disables the
generation of an external reset. Instead bit 1 of the INT_CAUS
register is set and an interrupt is generated
generation of an external reset. Instead bit 1 of the INT_CAUS
register is set and an interrupt is generated
0h = Test mode Disabled
1h = Test mode Enabled
1152
Watchdog Timer
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated