Texas Instruments CC2650DK 사용자 설명서
Modules
Table 17-6. Arithmetic and Logical Instructions (continued)
Syntax
Description
Operation
Z
N
C
V
xor Rd,Rs
XOR register
Rd ^= Rs
x
x
0
0
tst Rd,Rs
Test register
Rd & Rs
x
x
0
0
Monadic instructions
abs Rd
Absolute register
Rd = Rd > 0 ? Rd : - x
x
x
x
Rd
neg Rd
Negate register
Rd = -Rd
x
x
x
x
not Rd
Invert register
Rd = ~Rd
x
x
0
0
For instructions using an immediate operand, an 8-bit immediate is embedded in the instruction word.
Using the prefix-instruction, the immediate can be extended to a full 16-bit.
Using the prefix-instruction, the immediate can be extended to a full 16-bit.
The arithmetic add and cmp instructions treat the 8-bit immediate as a signed quantity, in other words in
the range of -128 to +127, sign-extending it to full register width as appropriate. This allows, for example,
immediate subtractions to be performed using the add instruction.
the range of -128 to +127, sign-extending it to full register width as appropriate. This allows, for example,
immediate subtractions to be performed using the add instruction.
The logical and, or, xor, and tst instructions treat the 8-bit immediate as an unsigned quantity, in other
words in the range of 0 to 255, zero-extending it to full register width as appropriate.
words in the range of 0 to 255, zero-extending it to full register width as appropriate.
For all operations, the Zero (Z) flag is set if the result is 0. The Negative (N) flag is set equal to the most
significant bit of the result.
significant bit of the result.
For arithmetic operations, the Carry (C) flag is set according to a carry or borrow out of the most
significant bit of the result. Similarly, the Overflow (V) flag is asserted if a arithmetic signed overflow
occurs.
significant bit of the result. Similarly, the Overflow (V) flag is asserted if a arithmetic signed overflow
occurs.
For logical operations, the Carry (C) and Overflow (V) flags are always both cleared.
17.4.1.5.5 Shift Operations
The shift operations operate on a destination operand in an integer register, while the source can be either
another integer register or a 3-bit immediate operand.
another integer register or a 3-bit immediate operand.
shows the shift instructions.
Table 17-7. Shift Instructions
Syntax
Description
Operation
Z
N
C
V
lsl Rd,Rs
Logical shift left
Rd <<= Rs
x
x
x
0
register
lsr Rd,Rs
Logical shift right
Rd >>= Rs
x
x
x
0
register
asr Rd,Rs
Arithmetic shift right
Rd >>= Rs, preserving sign
x
x
x
0
register
lsl Rd,#imm
Logical shift left
Rd <<= imm
x
x
x
0
immediate
lsr Rd,#imm
Logical shift right
Rd >>= imm
x
x
x
0
immediate
asr Rd,#imm
Arithmetic shift right
Rd >>= imm, preserving
x
x
x
0
immediate
sign
For instructions using an immediate operand, a 3-bit immediate is embedded in the instruction word,
allowing an immediate shift value in the range 1-8 to be encoded. Note that due to restrictions in the builtin
barrelshifter – to save area and power – shifts can only be in the range 0 to 15 positions, even when using
the register version of the instructions.
allowing an immediate shift value in the range 1-8 to be encoded. Note that due to restrictions in the builtin
barrelshifter – to save area and power – shifts can only be in the range 0 to 15 positions, even when using
the register version of the instructions.
For all operations, the Zero (Z) flag is set if the result is 0. The Negative (N) flag is set equal to the most
significant bit of the result. The Carry (C) flag is set according to the last bit shifted out, whether through
the most significant or least significant bit. The Overflow (V) flag is always cleared.
significant bit of the result. The Carry (C) flag is set according to the last bit shifted out, whether through
the most significant or least significant bit. The Overflow (V) flag is always cleared.
1195
SWCU117A – February 2015 – Revised March 2015
AUX – Sensor Controller with Digital and Analog Peripherals
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