Texas Instruments CC2650DK 사용자 설명서
Modules
The ADC is powered by VDDR internally, so the capacitive-input sampling stage will scale down the input
signal down within the reference range. The user can disable input scaling, but this requires that the
maximum input signal voltage to the ADC input is always lower than VDDR, to avoid permanent damage
to the ADC.
signal down within the reference range. The user can disable input scaling, but this requires that the
maximum input signal voltage to the ADC input is always lower than VDDR, to avoid permanent damage
to the ADC.
When scaling is enabled (default), the internal fixed reference will seem to be 4.3 V. If input scaling is
disabled, the reference will be 1.47 V.
disabled, the reference will be 1.47 V.
To save power in synchronous mode, the ADC reference can also be powered off during idle periods if the
sampling period is long enough to turn it on again during sampling, by setting
[AUX_ADI:ADCREF0.REF_ON_IDLE].
sampling period is long enough to turn it on again during sampling, by setting
[AUX_ADI:ADCREF0.REF_ON_IDLE].
The ADC reference source is selected in the [AUX_ADI:ADCREF0.SRC] register, and enabled in the
[AUX_ADI_ADCREF0.EN] register.
[AUX_ADI_ADCREF0.EN] register.
17.4.9.3 Configuration
For accurate low-jitter sampling in asynchronous mode, the software must ensure that SCLK_HF is
sourced from the 24-MHz XTAL before using the ADC.
sourced from the 24-MHz XTAL before using the ADC.
17.4.9.3.1 Sample Mode and Sample Duration
Sampling mode is configured in [AUX_ADI:ADC0.SMPL:MODE].
Synchronous sampling is done by starting a sampling when a trigger is received. The input is then
sampled for a period defined in [AUX_ADI:ADC0.SMPL_CYCLE_EXP] before a conversion is performed.
sampled for a period defined in [AUX_ADI:ADC0.SMPL_CYCLE_EXP] before a conversion is performed.
Asynchronous mode is always sampling, and only stops sampling when the start trigger occurs to perform
a conversion.
a conversion.
17.4.9.3.2
Input Signal Scaling
Disabling input scaling is configured through the [AUX_ADI:ADC1.SCALE_DIS] register, and can be used
to increase the ADC step resolution if the input signal is always below VDDR.
to increase the ADC step resolution if the input signal is always below VDDR.
Use this setting with caution, as any input voltage above VDDR might damage the ADC permanently.
17.4.9.3.3 ADC Enable
Enabling the ADC analog core is done by setting the bit [AUX_ADI:ADC0.EN]. This enables the internal
bias module and comparator.
bias module and comparator.
17.4.9.3.4 Digital Core
The SAR ADC has a digital core, used to configure the ADC and perform measurements as well as
interface the AUX registers for control and data.
interface the AUX registers for control and data.
After configuring the ADC registers in AUX_ADI, the ADC digital core can be enabled. Any changes to the
ADC core or reference configuration (except for the enable signals) requires the ADC digital core to be
reset again to take effect. This reset is done by clearing and then setting the reset signal in
[AUX_ADI:ADC0.RESET_N].
ADC core or reference configuration (except for the enable signals) requires the ADC digital core to be
reset again to take effect. This reset is done by clearing and then setting the reset signal in
[AUX_ADI:ADC0.RESET_N].
17.4.9.3.5 ADC Core Clock
The ADC core uses a 24-MHz clock source derived from SCLK_HF, which must be enabled by setting
[AUX_WUC:ADCCLKCTL.REQ]. When the corresponding ACK bit in the same register is read as high,
the clock is enabled to the ADC.
[AUX_WUC:ADCCLKCTL.REQ]. When the corresponding ACK bit in the same register is read as high,
the clock is enabled to the ADC.
17.4.9.4 Sampling
The ADC can start sampling on events from a number of different sources in AUX and AON, I/O events on
the AUX IOs, and the general purpose timers in MCU (through the event fabric).
the AUX IOs, and the general purpose timers in MCU (through the event fabric).
1206
AUX – Sensor Controller with Digital and Analog Peripherals
SWCU117A – February 2015 – Revised March 2015
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