Texas Instruments CC2650DK 사용자 설명서
Idle
Write slave
address to
I2C_MSA
Read I2C_MSTAT
Read I2C_MSTAT
BUSY bit = 0?
BUSY bit = 0?
ERR bit = 0?
Idle
Error service
Yes
No
Yes
No
Yes
No
Sequence may be
omitted in a
single master
system.
Write 0 t 011 to
I2C_MCTRL
ERR bit = 0?
Index = n?
ARBLST bit = 1?
Idle
Write data to
I2C_MDR
BUSY bit = 0?
Write 0 t 001 to
I2C_MCTRL
Write 0 t 101 to
I2C_MCTRL
Read I2C_MSTAT
Write data to
I2C_MDR
Error serivce
Write 0 t 100 to
I2C_MCTRL
No
No
Yes
Yes
Yes
No
Yes
No
Functional Description
Figure 21-9. Master TRANSMIT With Repeated Start Condition
1386
SWCU117A – February 2015 – Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
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