Texas Instruments CC2650DK 사용자 설명서
ADx (I2S)
MSB
BCLK
WCLK
LSB
MSB
Phase
WCLK and ADx are sampled at this edge
WCLK and ADx are clocked out at this edge
Slave
BCLK
WCLK
Master
ADx
ADx
Introduction
22.1 Introduction
The CC26xx device features an I2S module that supports the I2S, LJF, RJF, and DSP interface formats.
This interface can be used to transfer audio sample streams between CC26xx and external audio devices,
such as codecs, DACs, and ADCs. The CC26xx can act as either I2S master or I2S slave.
This interface can be used to transfer audio sample streams between CC26xx and external audio devices,
such as codecs, DACs, and ADCs. The CC26xx can act as either I2S master or I2S slave.
22.2 Digital Audio Interface
The I2S interface consists of the signals shown in
. The master provides the clock signals,
Word Clock (WCLK) and Bit Clock (BCLK), used for interface to the slave. Audio data is transferred
serially on the data lines, ADx (where x is 0, 1, or 2). The direction for each ADx pin may be from master
to slave or from slave to master, and is fixed during active operation. An optional Master Clock (MCLK)
signal can be provided from the master. The MCLK signal can be used as the master clock for external
audio codecs and so on.
serially on the data lines, ADx (where x is 0, 1, or 2). The direction for each ADx pin may be from master
to slave or from slave to master, and is fixed during active operation. An optional Master Clock (MCLK)
signal can be provided from the master. The MCLK signal can be used as the master clock for external
audio codecs and so on.
Figure 22-1. Audio Interface Signals
The supported interface formats are synchronous to the BCLK, and the words (samples) are aligned
according to the WCLK signal. WCLK is synchronous to BCLK signal, and for all supported interface
formats, the frequency of WCLK is the same as the sample frequency. The period from one positive
WCLK edge to the next positive WCLK edge is called a frame. Depending on the interface format, a frame
may consist of one or two phases.
according to the WCLK signal. WCLK is synchronous to BCLK signal, and for all supported interface
formats, the frequency of WCLK is the same as the sample frequency. The period from one positive
WCLK edge to the next positive WCLK edge is called a frame. Depending on the interface format, a frame
may consist of one or two phases.
Data is sampled on one edge of BCLK and updated on the opposite edge. The frequency of BCLK may be
any multiple of the frequency of WCLK, but the number of BCLK periods within a frame must at least be
equal to the number of bits produced or consumed within a sample period.
any multiple of the frequency of WCLK, but the number of BCLK periods within a frame must at least be
equal to the number of bits produced or consumed within a sample period.
If a format has two phases per frame (as in I2S, RJF, and LJF), it is said to be dual-phased.
shows an example of the signals used for the I2S interface format. In this case, WCLK is low during the
first phase and high during the second phase; hence, both edges are relevant for phase timing.
first phase and high during the second phase; hence, both edges are relevant for phase timing.
NOTE:
For the I2S interface format, the polarity of WCLK is inverted compared to RJF and LJF.
Figure 22-2. I2S Interface Format Example
The DSP interface format is a single-phased format. A single-phase format has one phase per frame, but
unlike the dual-phased formats, each frame can contain multiple data channels. In
unlike the dual-phased formats, each frame can contain multiple data channels. In
, an
example of the DSP interface format is presented. WCLK goes high for one BCLK period at the start of
the phase; therefore only the positive edge is relevant for phase timing. The WCLK cycle is followed by all
the data channels back-to-back. The data is updated on the positive edge of BCLK and sampled on the
negative edge.
the phase; therefore only the positive edge is relevant for phase timing. The WCLK cycle is followed by all
the data channels back-to-back. The data is updated on the positive edge of BCLK and sampled on the
negative edge.
1412
Integrated Interchip Sound (I2S) Module
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated