Texas Instruments CC2650DK 사용자 설명서
I2S Registers
22.10.1 I2S Registers
lists the memory-mapped registers for the I2S. All register offset addresses not listed in
should be considered as reserved locations and the register contents should not be modified.
Table 22-1. I2S Registers
Offset
Acronym
Register Name
Section
0h
AIFWCLKSRC
WCLK Source Selection
4h
AIFDMACFG
DMA Buffer Size Configuration
8h
AIFDIRCFG
Pin Direction
Ch
AIFFMTCFG
Serial Interface Format Configuration
10h
AIFWMASK0
Word Selection Bit Mask for Pin 0
14h
AIFWMASK1
Word Selection Bit Mask for Pin 1
18h
AIFWMASK2
Word Selection Bit Mask for Pin 2
1Ch
AIFPWMVALUE
Audio Interface PWM Debug Value
20h
AIFINPTRNEXT
DMA Input Buffer Next Pointer
24h
AIFINPTR
DMA Input Buffer Current Pointer
28h
AIFOUTPTRNEXT
DMA Output Buffer Next Pointer
2Ch
AIFOUTPTR
DMA Output Buffer Current Pointer
34h
STMPCTL
SampleStaMP Generator Control Register
38h
STMPXCNTCAPT0
Captured XOSC Counter Value, Capture Channel 0
3Ch
STMPXPER
XOSC Period Value
40h
STMPWCNTCAPT0
Captured WCLK Counter Value, Capture Channel 0
44h
STMPWPER
WCLK Counter Period Value
48h
STMPINTRIG
WCLK Counter Trigger Value for Input Pins
4Ch
STMPOUTTRIG
WCLK Counter Trigger Value for Output Pins
50h
STMPWSET
WCLK Counter Set Operation
54h
STMPWADD
WCLK Counter Add Operation
58h
STMPXPERMIN
XOSC Minimum Period Value
5Ch
STMPWCNT
Current Value of WCNT
60h
STMPXCNT
Current Value of XCNT
64h
STMPXCNTCAPT1
Captured XOSC Counter Value, Capture Channel 1
68h
STMPWCNTCAPT1
Captured WCLK Counter Value, Capture Channel 1
70h
IRQMASK
Masked Interrupt Status Register
74h
IRQFLAGS
Raw Interrupt Status Register
78h
IRQSET
Interrupt Set Register
7Ch
IRQCLR
Interrupt Clear Register
1423
SWCU117A – February 2015 – Revised March 2015
Integrated Interchip Sound (I2S) Module
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