Texas Instruments CC2650DK 사용자 설명서
I2S Registers
22.10.1.28 IRQFLAGS Register (Offset = 74h) [reset = X]
IRQFLAGS is shown in
and described in
Raw Interrupt Status Register
Figure 22-35. IRQFLAGS Register
31
30
29
28
27
26
25
24
RESERVED
R-X
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
RESERVED
R-X
7
6
5
4
3
2
1
0
RESERVED
AIF_DMA_IN
AIF_DMA_OUT
WCLK_TIMEO
BUS_ERR
WCLK_ERR
PTR_ERR
UT
R-X
R-X
R-X
R-X
R-X
R-X
R-X
Table 22-29. IRQFLAGS Register Field Descriptions
Bit
Field
Type
Reset
Description
31-6
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
5
AIF_DMA_IN
R
X
Set when condition for this bit field event occurs (auto cleared when
input pointer is updated - AIFINPTR), see description of AIFINPTR
register
input pointer is updated - AIFINPTR), see description of AIFINPTR
register
4
AIF_DMA_OUT
R
X
Set when condition for this bit field event occurs (auto cleared when
output pointer is updated - AIFOUTPTR), see description of
AIFOUTPTR register for details
output pointer is updated - AIFOUTPTR), see description of
AIFOUTPTR register for details
3
WCLK_TIMEOUT
R
X
Set when the sample stamp generator does not detect a positive
WCLK edge for 65535 clk periods. This signalizes that the internal or
external BCLK and WCLK generator source has been disabled. The
bit is sticky and may only be cleared by software (by writing '1' to
IRQCLR.WCLK_TIMEOUT).
WCLK edge for 65535 clk periods. This signalizes that the internal or
external BCLK and WCLK generator source has been disabled. The
bit is sticky and may only be cleared by software (by writing '1' to
IRQCLR.WCLK_TIMEOUT).
2
BUS_ERR
R
X
Set when a DMA operation is not completed in time (i.e. audio output
buffer underflow, or audio input buffer overflow). This error requires a
complete restart since word synchronization has been lost. The bit is
sticky and may only be cleared by software (by writing '1' to
IRQCLR.BUS_ERR). Note that DMA initiated transactions to illegal
addresses will not trigger an interrupt. The response to such
transactions is undefined.
buffer underflow, or audio input buffer overflow). This error requires a
complete restart since word synchronization has been lost. The bit is
sticky and may only be cleared by software (by writing '1' to
IRQCLR.BUS_ERR). Note that DMA initiated transactions to illegal
addresses will not trigger an interrupt. The response to such
transactions is undefined.
1
WCLK_ERR
R
X
Set when: - An unexpected WCLK edge occurs during the data
delay period of a phase. Note unexpected WCLK edges during the
word and idle periods of the phase are not detected. - In dual-phase
mode, when two WCLK edges are less than 4 BCLK cycles apart. -
In single-phase mode, when a WCLK pulse occurs before the last
channel. This error requires a complete restart since word
synchronization has been lost. The bit is sticky and may only be
cleared by software (by writing '1' to IRQCLR.WCLK_ERR).
delay period of a phase. Note unexpected WCLK edges during the
word and idle periods of the phase are not detected. - In dual-phase
mode, when two WCLK edges are less than 4 BCLK cycles apart. -
In single-phase mode, when a WCLK pulse occurs before the last
channel. This error requires a complete restart since word
synchronization has been lost. The bit is sticky and may only be
cleared by software (by writing '1' to IRQCLR.WCLK_ERR).
0
PTR_ERR
R
X
Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been
loaded with the next block address in time. This error requires a
complete restart since word synchronization has been lost. The bit is
sticky and may only be cleared by software (by writing '1' to
IRQCLR.PTR_ERR).
loaded with the next block address in time. This error requires a
complete restart since word synchronization has been lost. The bit is
sticky and may only be cleared by software (by writing '1' to
IRQCLR.PTR_ERR).
1451
SWCU117A – February 2015 – Revised March 2015
Integrated Interchip Sound (I2S) Module
Copyright © 2015, Texas Instruments Incorporated