Texas Instruments CC2650DK 사용자 설명서
RF Core HAL
For hardware registers, bits 2–15 give the address of the hardware register to access, see
.
The register will be written with a 32-bit write operation, but the 16 most significant bits are always written
as 0, while the 16 least significant bits are as given by value. To write a full 32-bit hardware register, use
an array operation of length 1.
as 0, while the 16 least significant bits are as given by value. To write a full 32-bit hardware register, use
an array operation of length 1.
An array initiator signals that the next words must be written to consecutive addresses, see
The type of accesses is decided by arrayType:
•
00 gives 32-bit writes to 16-bit hardware registers. The first register address is 0x4004 0000 +
(startAddr << 2). Then length addresses are written. Each value is taken from the next 16-bit half-word
of the override entry, and the register address is incremented by 4 each time a write occurs. If length is
odd, padding is assumed so that the first entry after the array is 32-bit word-aligned.
(startAddr << 2). Then length addresses are written. Each value is taken from the next 16-bit half-word
of the override entry, and the register address is incremented by 4 each time a write occurs. If length is
odd, padding is assumed so that the first entry after the array is 32-bit word-aligned.
•
01 gives 32-bit writes to hardware registers. The first register address is
0x4004 0000 + (startAddr << 2). Then length addresses are written. Each 32-bit value is taken from
the next 32-bit word of the override entry, and the register address is incremented by 4 each time a
write takes place.
0x4004 0000 + (startAddr << 2). Then length addresses are written. Each 32-bit value is taken from
the next 32-bit word of the override entry, and the register address is incremented by 4 each time a
write takes place.
•
10 gives byte writes to ADI registers. The first ADI bus address is given by bits 0–5 of startAddr. If bit 6
is 1, half-byte writes are used, otherwise full-byte writes (the least significant bit is ignored by the ADI
in this case). Bit 7 selects which ADI to write to. Each value written on the ADI bus is taken from the
next byte of the override entry, and the ADI register address is incremented by 1 in case of half-byte
writes or 2 in case of full-byte writes each time a write occurs. If length is not divisible by 4, padding is
assumed so that the first entry after the array is 32-bit word-aligned.
is 1, half-byte writes are used, otherwise full-byte writes (the least significant bit is ignored by the ADI
in this case). Bit 7 selects which ADI to write to. Each value written on the ADI bus is taken from the
next byte of the override entry, and the ADI register address is incremented by 1 in case of half-byte
writes or 2 in case of full-byte writes each time a write occurs. If length is not divisible by 4, padding is
assumed so that the first entry after the array is 32-bit word-aligned.
•
11 gives writes to firmware-defined parameters. The first index into the configuration values is given by
startAddr/4, and length bytes are copied from the override entry. If length is not divisible by 4, padding
is assumed so that the first entry after the array is 32-bit word-aligned.
startAddr/4, and length bytes are copied from the override entry. If length is not divisible by 4, padding
is assumed so that the first entry after the array is 32-bit word-aligned.
For ADI registers, adiValue gives the value to write and adiAddr gives the address on the ADI bus (see
). The ADI to write is selected through adiNo. If bHalfSize is 1, the write size bit on the ADI
interface is set, causing the value to be masked half size; otherwise, it is a full-size write, and the least
significant bit of the address is ignored. If adiAddr2 is nonzero, the value given by adiValue2 is written to
the ADI bus address given by adiAddr2; otherwise these two fields are ignored (if ADI address 0 is to be
written, it must be done through adiAddr/adiValue). In this case, bHalfSize and adiNo applies to both
writes.
significant bit of the address is ignored. If adiAddr2 is nonzero, the value given by adiValue2 is written to
the ADI bus address given by adiAddr2; otherwise these two fields are ignored (if ADI address 0 is to be
written, it must be done through adiAddr/adiValue). In this case, bHalfSize and adiNo applies to both
writes.
For radio firmware-defined parameters (see
), fwAddr gives a Byte Index into an array of
configuration values held in the radio. If bByte = 1, only the least significant byte of value is written to the
addressed byte. If bByte = 0, all 16 bits are written to the 16-bit half-word at the given byte address, which
must be even in this case. The selected value is set to the value specified in the value part of the override
entry.
addressed byte. If bByte = 0, all 16 bits are written to the 16-bit half-word at the given byte address, which
must be even in this case. The selected value is set to the value specified in the value part of the override
entry.
The first entry in the override list may contain an override of the MCE and RFE modes, as given by
. If so, the MCE is set to run from RAM if bMceUseRam is 1, otherwise from the ROM bank
given by mceRomBank. The value of MDMCMDPAR0 set when the CPE runs the MCE configuration
command given by mceMode. Similarly, the RFE is set to run from RAM if bRfeUseRam is 1, otherwise
from the ROM bank given by rfeRomBank. The value of RFECMDPAR0 set when the CPE runs the RFE
configuration command is given by rfeMode.
command given by mceMode. Similarly, the RFE is set to run from RAM if bRfeUseRam is 1, otherwise
from the ROM bank given by rfeRomBank. The value of RFECMDPAR0 set when the CPE runs the RFE
configuration command is given by rfeMode.
If the pointer in pRegOverride is invalid, any override entry is invalid, if the length of an array is too large
or zero, the operation ends with the status ERROR_PAR. If config.bNoFsPowerup = 0 and powering up
the synthesizer fails, the command ends with ERROR_SYNTH_PROG as the status.
or zero, the operation ends with the status ERROR_PAR. If config.bNoFsPowerup = 0 and powering up
the synthesizer fails, the command ends with ERROR_SYNTH_PROG as the status.
If CMD_ABORT or CMD_STOP is received while waiting for the start trigger, the operation ends without
any setup. If CMD_STOP is received after the start trigger, setup proceeds until finished. If CMD_ABORT
is received after the start trigger, the setup process will be aborted. This leaves the registers in an
incomplete state, so another CMD_RADIO_SETUP command must be issued before using the radio.
any setup. If CMD_STOP is received after the start trigger, setup proceeds until finished. If CMD_ABORT
is received after the start trigger, the setup process will be aborted. This leaves the registers in an
incomplete state, so another CMD_RADIO_SETUP command must be issued before using the radio.
1473
SWCU117A – February 2015 – Revised March 2015
Radio
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