Texas Instruments CC2650DK 사용자 설명서
Cortex-M3 Processor Registers
2.7.4.12 NVIC_ISPR1 Register (Offset = 204h) [reset = X]
NVIC_ISPR1 is shown in
and described in
.
Irq 32 to 63 Set Pending This register is used to force interrupts into the pending state and determine
which interrupts are currently pending.
which interrupts are currently pending.
Figure 2-82. NVIC_ISPR1 Register
31
30
29
28
27
26
25
24
RESERVED
R/W-X
23
22
21
20
19
18
17
16
RESERVED
R/W-X
15
14
13
12
11
10
9
8
RESERVED
R/W-X
7
6
5
4
3
2
1
0
RESERVED
SETPEND33
SETPEND32
R/W-X
R/W-X
R/W-X
Table 2-108. NVIC_ISPR1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-2
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
1
SETPEND33
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details).
Reading the bit returns its current state.
interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details).
Reading the bit returns its current state.
0
SETPEND32
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details).
Reading the bit returns its current state.
interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details).
Reading the bit returns its current state.
148
SWCU117A – February 2015 – Revised March 2015
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