Texas Instruments CC2650DK 사용자 설명서
Cortex-M3 Processor Registers
Table 2-109. NVIC_ICPR0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
CLRPEND2
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV
for details). Reading the bit returns its current state.
corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV
for details). Reading the bit returns its current state.
1
CLRPEND1
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV
for details). Reading the bit returns its current state.
corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV
for details). Reading the bit returns its current state.
0
CLRPEND0
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV
for details). Reading the bit returns its current state.
corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV
for details). Reading the bit returns its current state.
151
SWCU117A – February 2015 – Revised March 2015
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