Texas Instruments CC2650DK 사용자 설명서
Cortex-M3 Processor Registers
Table 2-111. NVIC_IABR0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
20
ACTIVE20
R
X
Reading 0 from this bit implies that interrupt line 20 is not active.
Reading 1 from this bit implies that the interrupt line 20 is active (See
EVENT:CPUIRQSEL20.EV for details).
Reading 1 from this bit implies that the interrupt line 20 is active (See
EVENT:CPUIRQSEL20.EV for details).
19
ACTIVE19
R
X
Reading 0 from this bit implies that interrupt line 19 is not active.
Reading 1 from this bit implies that the interrupt line 19 is active (See
EVENT:CPUIRQSEL19.EV for details).
Reading 1 from this bit implies that the interrupt line 19 is active (See
EVENT:CPUIRQSEL19.EV for details).
18
ACTIVE18
R
X
Reading 0 from this bit implies that interrupt line 18 is not active.
Reading 1 from this bit implies that the interrupt line 18 is active (See
EVENT:CPUIRQSEL18.EV for details).
Reading 1 from this bit implies that the interrupt line 18 is active (See
EVENT:CPUIRQSEL18.EV for details).
17
ACTIVE17
R
X
Reading 0 from this bit implies that interrupt line 17 is not active.
Reading 1 from this bit implies that the interrupt line 17 is active (See
EVENT:CPUIRQSEL17.EV for details).
Reading 1 from this bit implies that the interrupt line 17 is active (See
EVENT:CPUIRQSEL17.EV for details).
16
ACTIVE16
R
X
Reading 0 from this bit implies that interrupt line 16 is not active.
Reading 1 from this bit implies that the interrupt line 16 is active (See
EVENT:CPUIRQSEL16.EV for details).
Reading 1 from this bit implies that the interrupt line 16 is active (See
EVENT:CPUIRQSEL16.EV for details).
15
ACTIVE15
R
X
Reading 0 from this bit implies that interrupt line 15 is not active.
Reading 1 from this bit implies that the interrupt line 15 is active (See
EVENT:CPUIRQSEL15.EV for details).
Reading 1 from this bit implies that the interrupt line 15 is active (See
EVENT:CPUIRQSEL15.EV for details).
14
ACTIVE14
R
X
Reading 0 from this bit implies that interrupt line 14 is not active.
Reading 1 from this bit implies that the interrupt line 14 is active (See
EVENT:CPUIRQSEL14.EV for details).
Reading 1 from this bit implies that the interrupt line 14 is active (See
EVENT:CPUIRQSEL14.EV for details).
13
ACTIVE13
R
X
Reading 0 from this bit implies that interrupt line 13 is not active.
Reading 1 from this bit implies that the interrupt line 13 is active (See
EVENT:CPUIRQSEL13.EV for details).
Reading 1 from this bit implies that the interrupt line 13 is active (See
EVENT:CPUIRQSEL13.EV for details).
12
ACTIVE12
R
X
Reading 0 from this bit implies that interrupt line 12 is not active.
Reading 1 from this bit implies that the interrupt line 12 is active (See
EVENT:CPUIRQSEL12.EV for details).
Reading 1 from this bit implies that the interrupt line 12 is active (See
EVENT:CPUIRQSEL12.EV for details).
11
ACTIVE11
R
X
Reading 0 from this bit implies that interrupt line 11 is not active.
Reading 1 from this bit implies that the interrupt line 11 is active (See
EVENT:CPUIRQSEL11.EV for details).
Reading 1 from this bit implies that the interrupt line 11 is active (See
EVENT:CPUIRQSEL11.EV for details).
10
ACTIVE10
R
X
Reading 0 from this bit implies that interrupt line 10 is not active.
Reading 1 from this bit implies that the interrupt line 10 is active (See
EVENT:CPUIRQSEL10.EV for details).
Reading 1 from this bit implies that the interrupt line 10 is active (See
EVENT:CPUIRQSEL10.EV for details).
9
ACTIVE9
R
X
Reading 0 from this bit implies that interrupt line 9 is not active.
Reading 1 from this bit implies that the interrupt line 9 is active (See
EVENT:CPUIRQSEL9.EV for details).
Reading 1 from this bit implies that the interrupt line 9 is active (See
EVENT:CPUIRQSEL9.EV for details).
8
ACTIVE8
R
X
Reading 0 from this bit implies that interrupt line 8 is not active.
Reading 1 from this bit implies that the interrupt line 8 is active (See
EVENT:CPUIRQSEL8.EV for details).
Reading 1 from this bit implies that the interrupt line 8 is active (See
EVENT:CPUIRQSEL8.EV for details).
7
ACTIVE7
R
X
Reading 0 from this bit implies that interrupt line 7 is not active.
Reading 1 from this bit implies that the interrupt line 7 is active (See
EVENT:CPUIRQSEL7.EV for details).
Reading 1 from this bit implies that the interrupt line 7 is active (See
EVENT:CPUIRQSEL7.EV for details).
6
ACTIVE6
R
X
Reading 0 from this bit implies that interrupt line 6 is not active.
Reading 1 from this bit implies that the interrupt line 6 is active (See
EVENT:CPUIRQSEL6.EV for details).
Reading 1 from this bit implies that the interrupt line 6 is active (See
EVENT:CPUIRQSEL6.EV for details).
5
ACTIVE5
R
X
Reading 0 from this bit implies that interrupt line 5 is not active.
Reading 1 from this bit implies that the interrupt line 5 is active (See
EVENT:CPUIRQSEL5.EV for details).
Reading 1 from this bit implies that the interrupt line 5 is active (See
EVENT:CPUIRQSEL5.EV for details).
4
ACTIVE4
R
X
Reading 0 from this bit implies that interrupt line 4 is not active.
Reading 1 from this bit implies that the interrupt line 4 is active (See
EVENT:CPUIRQSEL4.EV for details).
Reading 1 from this bit implies that the interrupt line 4 is active (See
EVENT:CPUIRQSEL4.EV for details).
3
ACTIVE3
R
X
Reading 0 from this bit implies that interrupt line 3 is not active.
Reading 1 from this bit implies that the interrupt line 3 is active (See
EVENT:CPUIRQSEL3.EV for details).
Reading 1 from this bit implies that the interrupt line 3 is active (See
EVENT:CPUIRQSEL3.EV for details).
154
SWCU117A – February 2015 – Revised March 2015
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