Texas Instruments CC2650DK 사용자 설명서
Cortex-M3 Processor Registers
2.7.4.27 ICSR Register (Offset = D04h) [reset = X]
ICSR is shown in
and described in
Interrupt Control State This register is used to set a pending Non-Maskable Interrupt (NMI), set or clear a
pending SVC, set or clear a pending SysTick, check for pending exceptions, check the vector number of
the highest priority pended exception, and check the vector number of the active exception.
pending SVC, set or clear a pending SysTick, check for pending exceptions, check the vector number of
the highest priority pended exception, and check the vector number of the active exception.
Figure 2-97. ICSR Register
31
30
29
28
27
26
25
24
NMIPENDSET
RESERVED
PENDSVSET
PENDSVCLR
PENDSTSET
PENDSTCLR
RESERVED
R/W-X
R/W-X
R/W-X
W-0h
R/W-X
W-0h
R-X
23
22
21
20
19
18
17
16
ISRPREEMPT
ISRPENDING
RESERVED
VECTPENDING
R-X
R-X
R-X
R-X
15
14
13
12
11
10
9
8
VECTPENDING
RETTOBASE
RESERVED
VECTACTIVE
R-X
R-X
R-X
R-X
7
6
5
4
3
2
1
0
VECTACTIVE
R-X
Table 2-123. ICSR Register Field Descriptions
Bit
Field
Type
Reset
Description
31
NMIPENDSET
R/W
X
Set pending NMI bit. Setting this bit pends and activates an NMI.
Because NMI is the highest-priority interrupt, it takes effect as soon
as it registers. 0: No action 1: Set pending NMI
Because NMI is the highest-priority interrupt, it takes effect as soon
as it registers. 0: No action 1: Set pending NMI
30-29
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
28
PENDSVSET
R/W
X
Set pending pendSV bit. 0: No action 1: Set pending PendSV
27
PENDSVCLR
W
0h
Clear pending pendSV bit 0: No action 1: Clear pending pendSV
26
PENDSTSET
R/W
X
Set a pending SysTick bit. 0: No action 1: Set pending SysTick
25
PENDSTCLR
W
0h
Clear pending SysTick bit 0: No action 1: Clear pending SysTick
24
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
23
ISRPREEMPT
R
X
This field can only be used at debug time. It indicates that a pending
interrupt is to be taken in the next running cycle. If
DHCSR.C_MASKINTS= 0, the interrupt is serviced. 0: A pending
exception is not serviced. 1: A pending exception is serviced on exit
from the debug halt state
interrupt is to be taken in the next running cycle. If
DHCSR.C_MASKINTS= 0, the interrupt is serviced. 0: A pending
exception is not serviced. 1: A pending exception is serviced on exit
from the debug halt state
22
ISRPENDING
R
X
Interrupt pending flag. Excludes NMI and faults. 0x0: Interrupt not
pending 0x1: Interrupt pending
pending 0x1: Interrupt pending
21-18
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
17-12
VECTPENDING
R
X
Pending ISR number field. This field contains the interrupt number of
the highest priority pending ISR.
the highest priority pending ISR.
11
RETTOBASE
R
X
Indicates whether there are preempted active exceptions: 0: There
are preempted active exceptions to execute 1: There are no active
exceptions, or the currently-executing exception is the only active
exception.
are preempted active exceptions to execute 1: There are no active
exceptions, or the currently-executing exception is the only active
exception.
10-9
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
8-0
VECTACTIVE
R
X
Active ISR number field. Reset clears this field.
167
SWCU117A – February 2015 – Revised March 2015
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