Texas Instruments CC2650DK 사용자 설명서
Cortex-M3 Processor Registers
2.7.4.31 CCR Register (Offset = D14h) [reset = X]
CCR is shown in
and described in
.
Configuration Control This register is used to enable NMI, HardFault and FAULTMASK to ignore bus fault,
trap divide by zero and unaligned accesses, enable user access to the Software Trigger Interrupt Register
(STIR), control entry to Thread Mode.
trap divide by zero and unaligned accesses, enable user access to the Software Trigger Interrupt Register
(STIR), control entry to Thread Mode.
Figure 2-101. CCR Register
31
30
29
28
27
26
25
24
RESERVED
R/W-X
23
22
21
20
19
18
17
16
RESERVED
R/W-X
15
14
13
12
11
10
9
8
RESERVED
STKALIGN
BFHFNMIGN
R/W-X
R/W-1h
R/W-X
7
6
5
4
3
2
1
0
RESERVED
DIV_0_TRP
UNALIGN_TRP
RESERVED
USERSETMPE
NONBASETHR
ND
EDENA
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
Table 2-127. CCR Register Field Descriptions
Bit
Field
Type
Reset
Description
31-10
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
9
STKALIGN
R/W
1h
Stack alignment bit. 0: Only 4-byte alignment is guaranteed for the
SP used prior to the exception on exception entry. 1: On exception
entry, the SP used prior to the exception is adjusted to be 8-byte
aligned and the context to restore it is saved. The SP is restored on
the associated exception return.
SP used prior to the exception on exception entry. 1: On exception
entry, the SP used prior to the exception is adjusted to be 8-byte
aligned and the context to restore it is saved. The SP is restored on
the associated exception return.
8
BFHFNMIGN
R/W
X
Enables handlers with priority -1 or -2 to ignore data BusFaults
caused by load and store instructions. This applies to the HardFault,
NMI, and FAULTMASK escalated handlers: 0: Data BusFaults
caused by load and store instructions cause a lock-up 1: Data
BusFaults caused by load and store instructions are ignored. Set this
bit to 1 only when the handler and its data are in absolutely safe
memory. The normal use of this bit is to probe system devices and
bridges to detect problems.
caused by load and store instructions. This applies to the HardFault,
NMI, and FAULTMASK escalated handlers: 0: Data BusFaults
caused by load and store instructions cause a lock-up 1: Data
BusFaults caused by load and store instructions are ignored. Set this
bit to 1 only when the handler and its data are in absolutely safe
memory. The normal use of this bit is to probe system devices and
bridges to detect problems.
7-5
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
4
DIV_0_TRP
R/W
X
Enables faulting or halting when the processor executes an SDIV or
UDIV instruction with a divisor of 0: 0: Do not trap divide by 0. In this
mode, a divide by zero returns a quotient of 0. 1: Trap divide by 0.
The relevant Usage Fault Status Register bit is CFSR.DIVBYZERO.
UDIV instruction with a divisor of 0: 0: Do not trap divide by 0. In this
mode, a divide by zero returns a quotient of 0. 1: Trap divide by 0.
The relevant Usage Fault Status Register bit is CFSR.DIVBYZERO.
3
UNALIGN_TRP
R/W
X
Enables unaligned access traps: 0: Do not trap unaligned halfword
and word accesses 1: Trap unaligned halfword and word accesses.
The relevant Usage Fault Status Register bit is CFSR.UNALIGNED.
If this bit is set to 1, an unaligned access generates a UsageFault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of the value in UNALIGN_TRP.
and word accesses 1: Trap unaligned halfword and word accesses.
The relevant Usage Fault Status Register bit is CFSR.UNALIGNED.
If this bit is set to 1, an unaligned access generates a UsageFault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of the value in UNALIGN_TRP.
2
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
1
USERSETMPEND
R/W
X
Enables unprivileged software access to STIR: 0: User code is not
allowed to write to the Software Trigger Interrupt register (STIR). 1:
User code can write the Software Trigger Interrupt register (STIR) to
trigger (pend) a Main exception, which is associated with the Main
stack pointer.
allowed to write to the Software Trigger Interrupt register (STIR). 1:
User code can write the Software Trigger Interrupt register (STIR) to
trigger (pend) a Main exception, which is associated with the Main
stack pointer.
171
SWCU117A – February 2015 – Revised March 2015
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