Texas Instruments CC2650DK 사용자 설명서
Cortex-M3 Processor Registers
2.7.4.33 SHPR2 Register (Offset = D1Ch) [reset = X]
SHPR2 is shown in
and described in
System Handlers 8-11 Priority This register is used to prioritize the SVC handler. System Handlers are a
special class of exception handler that can have their priority set to any of the priority levels. Most can be
masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.
special class of exception handler that can have their priority set to any of the priority levels. Most can be
masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.
Figure 2-103. SHPR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PRI_11
RESERVED
R/W-X
R/W-X
Table 2-129. SHPR2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
PRI_11
R/W
X
Priority of system handler 11. SVCall
23-0
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
174
SWCU117A – February 2015 – Revised March 2015
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