Texas Instruments CC2650DK 사용자 설명서
Cortex-M3 Processor Registers
2.7.5 CPU_TPIU Registers
lists the memory-mapped registers for the CPU_TPIU. All register offset addresses not listed
in
should be considered as reserved locations and the register contents should not be
modified.
Table 2-157. CPU_TPIU Registers
Offset
Acronym
Register Name
Section
0h
SSPSR
Supported Sync Port Sizes
4h
CSPSR
Current Sync Port Size
10h
ACPR
Async Clock Prescaler
F0h
SPPR
Selected Pin Protocol
300h
FFSR
Formatter and Flush Status
304h
FFCR
Formatter and Flush Control
308h
FSCR
Formatter Synchronization Counter
FA0h
CLAIMMASK
Claim Tag Mask
FA0h
CLAIMSET
Claim Tag Set
FA4h
CLAIMTAG
Current Claim Tag
FA4h
CLAIMCLR
Claim Tag Clear
FC8h
DEVID
Device ID
207
SWCU117A – February 2015 – Revised March 2015
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