Texas Instruments CC2650DK 사용자 설명서
Cortex-M3 Processor Registers
2.7.5.7
FSCR Register (Offset = 308h) [reset = X]
FSCR is shown in
and described in
.
Formatter Synchronization Counter
Figure 2-137. FSCR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
FSCR
R-X
Table 2-164. FSCR Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
FSCR
R
X
The global synchronization trigger is generated by the Program
Counter (PC) Sampler block. This means that there is no
synchronization counter in the TPIU.
Counter (PC) Sampler block. This means that there is no
synchronization counter in the TPIU.
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SWCU117A – February 2015 – Revised March 2015
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