Texas Instruments CC2650DK 사용자 설명서
ATB
interface
Asynchronous FIFO
APB
interface
Trace out
(serializer)
Debug
ATB
slave
port
APB
slave
port
Serial wire
trace port
(SWO)
Overview
The flash patch and breakpoint unit (FPB) provides up to eight hardware breakpoint comparators that
debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the
program code in the CODE memory region. Remap functions enable patching of applications stored in a
read-only area of flash memory into another area of on-chip SRAM or flash memory. If a patch is required,
the application programs the FPB to remap a number of addresses. When those addresses are accessed,
the accesses are redirected to a remap table specified in the FPB configuration.
debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the
program code in the CODE memory region. Remap functions enable patching of applications stored in a
read-only area of flash memory into another area of on-chip SRAM or flash memory. If a patch is required,
the application programs the FPB to remap a number of addresses. When those addresses are accessed,
the accesses are redirected to a remap table specified in the FPB configuration.
For more information on the Cortex-M3 debug capabilities, see the ARM® Debug Interface V5
Architecture Specification.
Architecture Specification.
2.3.3 Trace Port Interface Unit
The trace port interface unit (TPIU) acts as a bridge between the Cortex-M3 trace data from the ITM, and
an off-chip trace port analyzer (see
an off-chip trace port analyzer (see
).
Figure 2-2. TPIU Block Diagram
2.3.4 Cortex-M3 System Component Details
The Cortex-M3 includes the following system components:
•
SysTick: A 24-bit count-down timer that can be used as a real-time operating system (RTOS) tick timer
or as a simple counter (see
or as a simple counter (see
, SysTick)
•
Nested Vectored Interrupt Controller (NVIC): An embedded interrupt controller (INTC) that supports
low-latency interrupt processing (see
low-latency interrupt processing (see
, NVIC)
•
System Control Block (SCB): The programming model interface to the processor, which provides
system implementation information and system control, including configuration, control, and reporting
of system exceptions (see
system implementation information and system control, including configuration, control, and reporting
of system exceptions (see
, SCB). Key control and status features of the processor are
managed centrally in SCB within the System Control Space (SCS).
2.4
Programming Model
This section describes the Cortex-M3 programming model. Information about the processor modes and
privilege levels for software execution and stacks is included in addition to the descriptions of the
individual core registers in
privilege levels for software execution and stacks is included in addition to the descriptions of the
individual core registers in
, Coretex-M3 Core Registers.
31
SWCU117A – February 2015 – Revised March 2015
The Cortex-M3 Processor
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