Texas Instruments CC2650DK 사용자 설명서
Interrupts and Events Registers
4.6.2.51 UDMACH1SSEL Register (Offset = 508h) [reset = X]
UDMACH1SSEL is shown in
and described in
.
Output Selection for DMA Channel 1 SREQ
Figure 4-60. UDMACH1SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
EV
R-X
R-31h
Table 4-66. UDMACH1SSEL Register Field Descriptions
Bit
Field
Type
Reset
Description
31-7
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
6-0
EV
R
31h
Read only selection value
31h = UART0 RX DMA single request, controlled by
UART0:DMACTL.RXDMAE
UART0:DMACTL.RXDMAE
335
SWCU117A – February 2015 – Revised March 2015
Interrupts and Events
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