Texas Instruments CC2650DK 사용자 설명서
Chapter 5
SWCU117A – February 2015 – Revised March 2015
JTAG Interface
This chapter describes the cJTAG and JTAG interface for on-chip debug support.
Table 5-1. References
ID
Description
IEEE Standard Test Access Port and Boundary Scan Architecture, IEEE Std 1149.1a
[1]
1993 and Supplement Std. 1149.1b 1994, The Institute of Electrical and Electronics
Engineers, Inc.
Engineers, Inc.
IEEE 1149.7 Standard for Reduced-Pin and Enhanced-Functionality Test Access Port
[2]
and Boundary-Scan Architecture
Topic
...........................................................................................................................
Page
5.1
Top Level Debug System
...................................................................................
5.2
cJTAG
.............................................................................................................
5.3
ICEPick™
........................................................................................................
5.4
ICEMelter™
......................................................................................................
5.5
Serial Wire Viewer (SWV)
...................................................................................
5.6
Halt In Boot (HIB)
..............................................................................................
5.7
Debug and Shutdown
........................................................................................
5.8
Debug Features Supported Through WUC TAP
....................................................
5.9
Profiler Register
...............................................................................................
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SWCU117A – February 2015 – Revised March 2015
JTAG Interface
Copyright © 2015, Texas Instruments Incorporated