Texas Instruments CC2650DK 사용자 설명서
Voltage domain (VD)
Voltage
regulator
Clock
Clock enable
Power domain (PD)
Clock gate
Periphial
Power domain (PD)
Clock gate
Periphial
Power domain (PD)
Clock gate
Periphial
Introduction
6.1
Introduction
Power and clock management (PRCM) in the CC26xx device is highly flexible to facilitate low-power
applications. The following sections describe details for clock and power control in addition to covering
reset features.
applications. The following sections describe details for clock and power control in addition to covering
reset features.
The features in this chapter are embedded and optimized in TI-RTOS. TI-RTOS users may regard this
chapter as informative only.
chapter as informative only.
Figure 6-1. Hierarchy of Power-Saving Features
shows the hierarchy of power-saving features in the CC26xx device. Low-power consumption
and cycling time for a power-saving mode is inversely proportional. The power-saving mode with the
lowest-power consumption requires the longest time from initiation to power-saving mode, as well as
wake-up time back to Active mode.
lowest-power consumption requires the longest time from initiation to power-saving mode, as well as
wake-up time back to Active mode.
summarizes the power-saving features.
Table 6-1. Power Saving Features
Power Saving Feature
Description
Clock gating
Immediate response – no latency
Offers the least amount of power saved
Offers the least amount of power saved
Power domain off
Power cycling down and up takes longer time than clock gating. Modules in power domains without
(overrides clock gating)
retention must be reinitialized before functionality can be resumed.
Voltage domain off
Power cycling down and up takes longer time than PD power off. All modules in the voltage domain
must be reinitialized before functionality can be resumed.
must be reinitialized before functionality can be resumed.
Voltage regulator off
Power cycling down and up takes longer time than VD power off. Chip loses all configurations and will
boot at wakeup. Gives the least possible current consumption.
boot at wakeup. Gives the least possible current consumption.
lists the four defined power modes for the power-saving features in TI-RTOS, as shown in
. The power modes are discussed in detail in, Power Modes.
Table 6-2. Power Modes in TI-RTOS
Power Mode
Description
Active mode
The system CPU is running.
Idle mode
The power domain in which CPU resides is off.
Standby mode
All power domains are powered off and voltage domains are supplied by the micro LDO.
Shutdown mode
Only I/Os maintain their operation. All voltage regulators, voltage, and power domains are off.
412
Power, Reset, and Clock Management
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated