Texas Instruments CC2650DK 사용자 설명서
Introduction
6.1.6 Reset
The CC26xx device has several sources of reset, some are triggered due to errors or unexpected
behavior, while others is user initiated.
Resets may result in reset of:
behavior, while others is user initiated.
Resets may result in reset of:
•
The entire chip
•
A power domain
•
A voltage domain
•
A single digital module for debug purposes
6.1.6.1
System Resets
A reset resulting in a complete power-up sequence and system CPU boot sequence is defined a system
reset. The [AON_SYSCTL:RESETCTL.RESET_SRC] register is readable and will always show the last
source of a reset resulting in a system reset.
reset. The [AON_SYSCTL:RESETCTL.RESET_SRC] register is readable and will always show the last
source of a reset resulting in a system reset.
The following resets cannot be disabled and, when triggered, always result in a system reset:
•
Power-on reset
•
Pin reset
•
VDDS failure
•
VDDR failure
•
VDD failure
6.1.6.1.1 Clock Loss Detection
When the clock loss feature is enabled with the [DDI_0_OSC:CTL0.CLK_LOSS_EN] and the
[AON_SYSCTL.RESETCTL.CLK_LOSS_EN] registers, a detected loss of SCLK_LF will result in a system
reset. After recovery, the [AON_SYSCTL:RESETCTL.RESET_SRC] register will show clock loss as the
source of reset.
[AON_SYSCTL.RESETCTL.CLK_LOSS_EN] registers, a detected loss of SCLK_LF will result in a system
reset. After recovery, the [AON_SYSCTL:RESETCTL.RESET_SRC] register will show clock loss as the
source of reset.
6.1.6.1.2 Software-Initiated System Reset
Writing to the [AON_SYSCTL:RESETCTL.SYSRESET] register will result in a system reset. After
recovery, the [AON_SYSCTL:RESETCTL.RESET_SRC] register will show SYSRESET as the source of
reset.
recovery, the [AON_SYSCTL:RESETCTL.RESET_SRC] register will show SYSRESET as the source of
reset.
6.1.6.1.3 Warm Reset Converted to System Reset
Warm reset can be programmed with the [PRCM:WARMRESET.WR_TO_PINRESET] register to result in
a system reset when any warm reset source is triggered (see
a system reset when any warm reset source is triggered (see
). TI strongly recommends
enabling the Warm Reset Converted to System Reset feature.
6.1.6.2
Warm Reset
A reset that results in a reset of the MCU_VD and the system CPU bus part of AUX_PD, is defined as a
warm reset. A warm reset will leave all analog configurations unchanged while the system CPU and all
other digital modules in MCU_VD will be reset.
warm reset. A warm reset will leave all analog configurations unchanged while the system CPU and all
other digital modules in MCU_VD will be reset.
The following sources will initiate a warm reset generation:
•
The [CPU_SCS:AIRCR.SYSRESETREQ] register
•
System CPU LOCKUP
•
Watchdog time-out
When a warm reset source is triggered, MCU_VD is reset through a controlled sequence, returning
MCU_VD to the same state as when finishing a boot from system reset.
MCU_VD to the same state as when finishing a boot from system reset.
The [PRCM:WARMRESET] register has readable bits that indicate if the MCU_VD was reset due to a
system CPU LOCKUP event or a watchdog time-out.
system CPU LOCKUP event or a watchdog time-out.
426
Power, Reset, and Clock Management
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated