Texas Instruments CC2650DK 사용자 설명서
PRCM Registers
6.2.1.4
VDCTL Register (Offset = Ch) [reset = X]
VDCTL is shown in
and described in
.
MCU Voltage Domain Control
Figure 6-10. VDCTL Register
31
30
29
28
27
26
25
24
RESERVED
R/W-X
23
22
21
20
19
18
17
16
RESERVED
R/W-X
15
14
13
12
11
10
9
8
RESERVED
R/W-X
7
6
5
4
3
2
1
0
RESERVED
MCU_VD
RESERVED
ULDO
R/W-X
R/W-X
R/W-X
R/W-X
Table 6-12. VDCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
31-3
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
2
MCU_VD
R/W
X
Request WUC to power down the MCU voltage domain 0: No
request 1: Assert request when possible. An asserted power down
request will result in a boot of the MCU system when powered up
again. The bit will have no effect before the following requirements
are met: 1. PDCTL1.CPU_ON = 0 2. PDCTL1.VIMS_MODE = 0 3.
SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be loaded
with CLKLOADCTL.LOAD) 4. SECDMACLKGDS.CRYPTO_CLK_EN
= 0 (Note: Setting must be loaded with CLKLOADCTL.LOAD) 5.
RFC do no request access to BUS 6. System CPU in deepsleep
request 1: Assert request when possible. An asserted power down
request will result in a boot of the MCU system when powered up
again. The bit will have no effect before the following requirements
are met: 1. PDCTL1.CPU_ON = 0 2. PDCTL1.VIMS_MODE = 0 3.
SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be loaded
with CLKLOADCTL.LOAD) 4. SECDMACLKGDS.CRYPTO_CLK_EN
= 0 (Note: Setting must be loaded with CLKLOADCTL.LOAD) 5.
RFC do no request access to BUS 6. System CPU in deepsleep
1
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
0
ULDO
R/W
X
Request WUC to switch to uLDO. 0: No request 1: Assert request
when possible The bit will have no effect before the following
requirements are met: 1. PDCTL1.CPU_ON = 0 2.
PDCTL1.VIMS_MODE = 0 3. SECDMACLKGDS.DMA_CLK_EN = 0
(Note: Setting must be loaded with CLKLOADCTL.LOAD) 4.
SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be
loaded with CLKLOADCTL.LOAD) 5. RFC do no request access to
BUS 6. System CPU in deepsleep
when possible The bit will have no effect before the following
requirements are met: 1. PDCTL1.CPU_ON = 0 2.
PDCTL1.VIMS_MODE = 0 3. SECDMACLKGDS.DMA_CLK_EN = 0
(Note: Setting must be loaded with CLKLOADCTL.LOAD) 4.
SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be
loaded with CLKLOADCTL.LOAD) 5. RFC do no request access to
BUS 6. System CPU in deepsleep
433
SWCU117A – February 2015 – Revised March 2015
Power, Reset, and Clock Management
Copyright © 2015, Texas Instruments Incorporated