Texas Instruments CC2650DK 사용자 설명서
PRCM Registers
6.2.1.22 UARTCLKGDS Register (Offset = 74h) [reset = X]
UARTCLKGDS is shown in
and described in
.
UART Clock Gate For Deep Sleep Mode
Figure 6-28. UARTCLKGDS Register
31
30
29
28
27
26
25
24
RESERVED
R/W-X
23
22
21
20
19
18
17
16
RESERVED
R/W-X
15
14
13
12
11
10
9
8
RESERVED
R/W-X
7
6
5
4
3
2
1
0
RESERVED
CLK_EN
R/W-X
R/W-X
Table 6-30. UARTCLKGDS Register Field Descriptions
Bit
Field
Type
Reset
Description
31-1
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
0
CLK_EN
R/W
X
0: Disable clock 1: Enable clock For changes to take effect,
CLKLOADCTL.LOAD needs to be written
CLKLOADCTL.LOAD needs to be written
451
SWCU117A – February 2015 – Revised March 2015
Power, Reset, and Clock Management
Copyright © 2015, Texas Instruments Incorporated