Texas Instruments CC2650DK 사용자 설명서
PRCM Registers
6.2.3.9
CTL1 Register (Offset = 24h) [reset = X]
CTL1 is shown in
and described in
Control 1 This register contains various chip level control and debug bitfields.
Figure 6-75. CTL1 Register
31
30
29
28
27
26
25
24
RESERVED
R/W-X
23
22
21
20
19
18
17
16
RESERVED
R/W-X
15
14
13
12
11
10
9
8
RESERVED
R/W-X
7
6
5
4
3
2
1
0
RESERVED
MCU_RESET_
MCU_WARM_
SRC
RESET
R/W-X
R/W1C-X
R/W1C-X
Table 6-79. CTL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-2
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
1
MCU_RESET_SRC
R/W1C
X
Indicates source of last MCU Voltage Domain warm reset request: 0:
MCU SW reset 1: JTAG reset This bit can only be cleared by writing
a 1 to it
MCU SW reset 1: JTAG reset This bit can only be cleared by writing
a 1 to it
0
MCU_WARM_RESET
R/W1C
X
Indicates type of last MCU Voltage Domain reset: 0: Last MCU reset
was not a warm reset 1: Last MCU reset was a warm reset
(requested from MCU or JTAG as indicated in MCU_RESET_SRC)
This bit can only be cleared by writing a 1 to it
was not a warm reset 1: Last MCU reset was a warm reset
(requested from MCU or JTAG as indicated in MCU_RESET_SRC)
This bit can only be cleared by writing a 1 to it
502
Power, Reset, and Clock Management
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated