Texas Instruments CC2650DK 사용자 설명서
VIMS Registers
7.3.1 STAT Register (Offset = 0h) [reset = X]
STAT is shown in
and described in
Status Displays current VIMS mode and line buffer status
Figure 7-9. STAT Register
31
30
29
28
27
26
25
24
RESERVED
R-X
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
RESERVED
R-X
7
6
5
4
3
2
1
0
RESERVED
IDCODE_LB_D SYSBUS_LB_D
MODE_CHAN
INV
MODE
IS
IS
GING
R-X
R-X
R-X
R-X
R-X
R-X
Table 7-3. STAT Register Field Descriptions
Bit
Field
Type
Reset
Description
31-6
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
5
IDCODE_LB_DIS
R
X
Icode/Dcode flash line buffer status 0: Enabled or in transition to
disabled 1: Disabled and flushed
disabled 1: Disabled and flushed
4
SYSBUS_LB_DIS
R
X
Sysbus flash line buffer control 0: Enabled or in transition to disabled
1: Disabled and flushed
1: Disabled and flushed
3
MODE_CHANGING
R
X
VIMS mode change status 0: VIMS is in the mode defined by MODE
1: VIMS is in the process of changing to the mode given in
CTL.MODE
1: VIMS is in the process of changing to the mode given in
CTL.MODE
2
INV
R
X
This bit is set when invalidation of the cache memory is active /
ongoing
ongoing
1-0
MODE
R
X
Current VIMS mode
0h = GPRAM : VIMS GPRAM mode
1h = CACHE : VIMS Cache mode
2h = VIMS Split Cache mode
3h = VIMS Off mode
538
Versatile Instruction Memory System (VIMS)
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated