Texas Instruments CC2650DK 사용자 설명서
Customer Configuration (CCFG)
9.1.1.6
RTC_OFFSET Register (Offset = FC0h) [reset = FFFFFFFFh]
RTC_OFFSET is shown in
and described in
Real Time Clock Offset Enabled by MODE_CONF.RTC_COMP.
Figure 9-6. RTC_OFFSET Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RTC_COMP_P0
R/W-FFFFh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RTC_COMP_P1
RTC_COMP_P2
R/W-FFh
R/W-FFh
Table 9-7. RTC_OFFSET Register Field Descriptions
Bit
Field
Type
Reset
Description
31-16
RTC_COMP_P0
R/W
FFFFh
Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.
reserved. Writing any other value than the reset/default value may
result in undefined behavior.
15-8
RTC_COMP_P1
R/W
FFh
Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.
reserved. Writing any other value than the reset/default value may
result in undefined behavior.
7-0
RTC_COMP_P2
R/W
FFh
Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.
reserved. Writing any other value than the reset/default value may
result in undefined behavior.
694
Device Configuration
SWCU117A – February 2015 – Revised March 2015
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