Texas Instruments CC2650DK 사용자 설명서
Factory Configuration (FCFG)
9.2.1 FCFG1 Registers
lists the memory-mapped registers for the FCFG1. All register offset addresses not listed in
should be considered as reserved locations and the register contents should not be modified.
Table 9-23. FCFG1 Registers
Offset
Acronym
Register Name
Section
C4h
CONFIG_RF_FRONTEND_DIV5
Configuration of RF Frontend in Divide-by-5 Mode
C8h
CONFIG_RF_FRONTEND_DIV6
Configuration of RF Frontend in Divide-by-6 Mode
CCh
CONFIG_RF_FRONTEND_DIV10
Configuration of RF Frontend in Divide-by-10 Mode
D0h
CONFIG_RF_FRONTEND_DIV12
Configuration of RF Frontend in Divide-by-12 Mode
D4h
CONFIG_RF_FRONTEND_DIV15
Configuration of RF Frontend in Divide-by-15 Mode
D8h
CONFIG_RF_FRONTEND_DIV30
Configuration of RF Frontend in Divide-by-30 Mode
DCh
CONFIG_SYNTH_DIV5
Configuration of Synthesizer in Divide-by-5 Mode
E0h
CONFIG_SYNTH_DIV6
Configuration of Synthesizer in Divide-by-6 Mode
E4h
CONFIG_SYNTH_DIV10
Configuration of Synthesizer in Divide-by-10 Mode
E8h
CONFIG_SYNTH_DIV12
Configuration of Synthesizer in Divide-by-12 Mode
ECh
CONFIG_SYNTH_DIV15
Configuration of Synthesizer in Divide-by-15 Mode
F0h
CONFIG_SYNTH_DIV30
Configuration of Synthesizer in Divide-by-30 Mode
F4h
CONFIG_MISC_ADC_DIV5
Configuration of IFADC in Divide-by-5 Mode
F8h
CONFIG_MISC_ADC_DIV6
Configuration of IFADC in Divide-by-6 Mode
FCh
CONFIG_MISC_ADC_DIV10
Configuration of IFADC in Divide-by-10 Mode
100h
CONFIG_MISC_ADC_DIV12
Configuration of IFADC in Divide-by-12 Mode
104h
CONFIG_MISC_ADC_DIV15
Configuration of IFADC in Divide-by-15 Mode
108h
CONFIG_MISC_ADC_DIV30
Configuration of IFADC in Divide-by-30 Mode
118h
SHDW_DIE_ID_0
Shadow of [JTAG_TAP::EFUSE:DIE_ID_0.*]
11Ch
SHDW_DIE_ID_1
Shadow of [JTAG_TAP::EFUSE:DIE_ID_1.*]
120h
SHDW_DIE_ID_2
Shadow of [JTAG_TAP::EFUSE:DIE_ID_2.*]
124h
SHDW_DIE_ID_3
Shadow of [JTAG_TAP::EFUSE:DIE_ID_3.*]
138h
SHDW_OSC_BIAS_LDO_TRIM
Shadow of
[JTAG_TAP::EFUSE:OSC_BIAS_LDO_TRIM.*]
13Ch
SHDW_ANA_TRIM
Shadow of [JTAG_TAP::EFUSE:ANA_TRIM.*]
164h
FLASH_NUMBER
16Ch
FLASH_COORDINATE
170h
FLASH_E_P
Flash Erase and Program Setup Time
174h
FLASH_C_E_P_R
Flash Compaction, Execute, Program and Read
178h
FLASH_P_R_PV
Flash Program, Read, and Program Verify
17Ch
FLASH_EH_SEQ
Flash Erase Hold and Sequence
180h
FLASH_VHV_E
Flash VHV Erase
184h
FLASH_PP
Flash Program Pulse
188h
FLASH_PROG_EP
Flash Program and Erase Pulse
18Ch
FLASH_ERA_PW
Flash Erase Pulse Width
190h
FLASH_VHV
Flash VHV
194h
FLASH_VHV_PV
Flash VHV Program Verify
198h
FLASH_V
Flash Voltages
294h
USER_ID
User Identification
2B0h
FLASH_OTP_DATA3
Flash OTP Data 3
2B4h
ANA2_TRIM
Misc Analog Trim
2B8h
LDO_TRIM
LDO Trim
2E8h
MAC_BLE_0
MAC BLE Address 0
2ECh
MAC_BLE_1
MAC BLE Address 1
714 Device Configuration
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated