Texas Instruments CC2650DK 사용자 설명서
Factory Configuration (FCFG)
9.2.1.60 SOC_ADC_EXT_GAIN Register (Offset = 364h) [reset = 0h]
SOC_ADC_EXT_GAIN is shown in
and described in
AUX_ADC Gain in External Reference Mode
Figure 9-81. SOC_ADC_EXT_GAIN Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SOC_ADC_EXT_GAIN_TEMP2
R-0h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOC_ADC_EXT_GAIN_TEMP1
R-0h
Table 9-83. SOC_ADC_EXT_GAIN Register Field Descriptions
Bit
Field
Type
Reset
Description
31-16
SOC_ADC_EXT_GAIN_T
R
0h
SOC_ADC gain in external reference mode at temperature 2 (85C).
EMP2
Calculated in production test..
Reset holds trim value from production test.
15-0
SOC_ADC_EXT_GAIN_T
R
0h
SOC_ADC gain in external reference mode at temperature 1 (30C).
EMP1
Calculated in production test..
Reset holds trim value from production test.
777
SWCU117A – February 2015 – Revised March 2015
Device Configuration
Copyright © 2015, Texas Instruments Incorporated