Texas Instruments CC2650DK 사용자 설명서
Factory Configuration (FCFG)
9.2.1.79 PWD_CURR_125C Register (Offset = 3B8h) [reset = ADE1809Ah]
PWD_CURR_125C is shown in
and described in
Power Down Current Control 125C
Figure 9-100. PWD_CURR_125C Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DELTA_CACHE_REF
DELTA_RFMEM_RET
R-ADh
R-E1h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DELTA_XOSC_LPM
BASELINE
R-80h
R-9Ah
Table 9-102. PWD_CURR_125C Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
DELTA_CACHE_REF
R
ADh
Additional maximum current, in units of 1uA, with cache retention
23-16
DELTA_RFMEM_RET
R
E1h
Additional maximum current, in 1uA units, with RF memory retention
15-8
DELTA_XOSC_LPM
R
80h
Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode
low-power mode
7-0
BASELINE
R
9Ah
Worst-case baseline maximum powerdown current, in units of 0.5uA
796
Device Configuration
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated