Texas Instruments CC2650DK 사용자 설명서
20
Synchronous Serial Interface (SSI)
....................................................................................
20.1
Synchronous Serial Interface
..........................................................................................
20.2
Block Diagram
...........................................................................................................
20.3
Signal Description
.......................................................................................................
20.4
Functional Description
..................................................................................................
20.4.1
Bit Rate Generation
...........................................................................................
20.4.2
FIFO Operation
................................................................................................
20.4.3
Interrupts
.......................................................................................................
20.4.4
Frame Formats
................................................................................................
20.5
DMA Operation
..........................................................................................................
20.6
Initialization and Configuration
.........................................................................................
20.7
SSI Registers
............................................................................................................
20.7.1
SSI Registers
..................................................................................................
21
Inter-Integrated Circuit (I
2
C) Interface
................................................................................
21.1
Inter-Integrated Circuit Interface
.......................................................................................
21.2
Block Diagram
...........................................................................................................
21.3
Functional Description
..................................................................................................
21.3.1
I
2
C Bus Functional Overview
................................................................................
21.3.2
Available Speed Modes
......................................................................................
21.3.3
Interrupts
.......................................................................................................
21.3.4
Loopback Operation
..........................................................................................
21.3.5
Command Sequence Flow Charts
..........................................................................
21.4
Initialization and Configuration
.........................................................................................
21.5
I
2
C Registers
.............................................................................................................
21.5.1
I2C Registers
..................................................................................................
22
Integrated Interchip Sound (I2S) Module
............................................................................
22.1
Introduction
..............................................................................................................
22.2
Digital Audio Interface
..................................................................................................
22.3
Frame Configuration
....................................................................................................
22.4
Pin Configuration
........................................................................................................
22.5
Clock Configuration
.....................................................................................................
22.5.1
WCLK, BCLK, and MCLK Division Ratio
...................................................................
22.6
Serial Interface Formats
................................................................................................
22.6.1
I2S
...............................................................................................................
22.6.2
Left Justified (LJF)
............................................................................................
22.6.3
Right Justified (RJF)
..........................................................................................
22.6.4
DSP
.............................................................................................................
22.7
Memory Interface
........................................................................................................
22.7.1
Word Lengths
..................................................................................................
22.7.2
Audio Channels
................................................................................................
22.7.3
Memory Buffers and Pointers
................................................................................
22.8
Samplestamp Generator
...............................................................................................
22.8.1
Counters and Registers
......................................................................................
22.8.2
Starting Input and Output Pins
..............................................................................
22.8.3
Samplestamp Capturing
......................................................................................
22.9
Usage
.....................................................................................................................
22.9.1
Start-up Sequence
............................................................................................
22.9.2
Termination Sequence
.......................................................................................
22.10
I2S Registers
............................................................................................................
22.10.1
I2S Registers
.................................................................................................
23
Radio
.............................................................................................................................
23.1
RF Core
...................................................................................................................
8
Contents
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated