Texas Instruments CC2650DK 사용자 설명서

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AES Cryptoprocessor Overview

Table 10-1. Detailed Memory Map (continued)

Physical Address

Register Name

Type

Reset Value

Remark

Link

0x4002 407C

DMAPORTERR

R

0x0000 0000

Port-error raw-status

Section 10.2.1.10

register

0x4002 40F8

DMAHWOPT

R

0x0000 0202

DMAC-options
register

0x4002 40FC

DMAHWVER

R

0x0101 2ED1

DMAC-version

Section 10.2.1.11

register

Key-Storage Registers

0x4002 4400

KEYWRITEAREA

R/W

0x0000 0000

Writer-area register

Section 10.2.1.12

0x4002 4404

KEYWRITTENAREA

R/W

0x0000 0000

Written-area register

Section 10.2.1.13

0x4002 4408

KEYSIZE

R/W

0x0000 0001

Key-size register

Section 10.2.1.14

0x4002 440C

KEYREADAREA

R/W

0x0000 0008

Read-area register

Section 10.2.1.15

AES Engine Registers

0x4002 4500-

AESKEY2_0 to AESKEY2_3

W

0x0000 0000

Clear/wipe

0x4002 450C

AESKEY2__0 -

Section 10.2.1.16

AESKEY2__3
register

0x4002 4510-

AESKEY3_0 to AESKEY3_3

W

0x0000 0000

Clear/wipe

0x4002 451C

AESKEY3__0 -

Section 10.2.1.17

AESKEY3__3
register

0x4002 4540-

AESIV_0 to AESIV_3

R/W

0x0000 0000

AES IV (LSW)

Section 10.2.1.18

0x4002 454C

0x4002 4550

AESCTL

R/W

0x8000 0000

Input/Output and

Section 10.2.1.19

control mode

0x4002 4554

AESDATALEN0

W

0x0000 0000

Crypto data length

Section 10.2.1.20

(LSW)

0x4002 4558

AESDATALEN1

W

0x0000 0000

Crypto data length

Section 10.2.1.21

(MSW)

0x4002 455C

AESAUTHLEN

W

0x0000 0000

AAD data length

Section 10.2.1.22

0x4002 4560

AESDATAIN0

W

0x0000 0000

Data input (LSW)

Section 10.2.1.24

0x4002 4560

AESDATAOUT0

R

0x0000 0000

Data output (LSW)

Section 10.2.1.23

0x4002 4564

AESDATAIN1

W

0x0000 0000

Data input

Section 10.2.1.26

0x4002 4564

AESDATAOUT1

R

0x0000 0000

Data output

Section 10.2.1.25

0x4002 4568

AESDATAIN2

W

0x0000 0000

Data input

Section 10.2.1.28

0x4002 4568

AESDATAOUT2

R

0x0000 0000

Data output

Section 10.2.1.27

0x4002 456C

AESDATAIN3

W

0x0000 0000

Data input (MSW)

Section 10.2.1.30

0x4002 456C

AESDATAOUT3

R

0x0000 0000

Data output (MSW)

Section 10.2.1.29

0x4002 4570-

AESTAGOUT_0 to

W

0x0000 0000

Tag output (LSW)

Section 10.2.1.31

0x4002 4057C

AESTAGOUT_3

Master-Control Registers

0x4002 4700

ALGSEL

R/W

0x0000 0000

Algorithm selection

Section 10.2.1.32

0x4002 4704

DMAPROTCTL

R/W

0x0000 0000

Enable privileged

Section 10.2.1.33

access on master

0x4002 4740

SWRESET

W

0x0000 0000

Master-control

Section 10.2.1.34

software reset

0x4002 4780

IRQTYPE

R/W

0x0000 0000

Interrupt-

Section 10.2.1.35

configuration register

0x4002 4784

IRQEN

R/W

0x0000 0000

Interrupt-enabling

Section 10.2.1.36

register

0x4002 4788

IRQCLR

W

0x0000 0000

Interrupt-clear

Section 10.2.1.37

register

0x4002 478C

IRQSET

W

0x0000 0000

Interrupt-set register

Section 10.2.1.38

0x4002 4790

IRQSTAT

R

0x0000 0000

Interrupt-status

Section 10.2.1.39

register

801

SWCU117A – February 2015 – Revised March 2015

Cryptography

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