Texas Instruments CC2650DK 사용자 설명서
AES Cryptoprocessor Overview
10.1.5.2 Performance
shows the performance of the AES module running at 200 MHz for DMA-based cryptographic
operations.
Table 10-9. Performance Table for DMA-Based Operations
Performance in Mbps
Raw engine
1 block packet
20-block
100-block
Crypto-mode
performance
performance
(1)
performance
(1)
performance
(1)
AES-128 (1 block = 128 bits)
AES-128-ECB
79
18
67
76
AES-128-CBC
77
17
65
75
AES-128-CTR
79
17
66
76
(1)
The performance assumes full programming of the engine, loading keys, and setting up the DMA engine through the DMA slave.
If the context is reused (mode or keys), the performance is increased. The maximum number of cycles overhead per packet is
between 100 and 150 for the various modes and algorithms.
If the context is reused (mode or keys), the performance is increased. The maximum number of cycles overhead per packet is
between 100 and 150 for the various modes and algorithms.
The engine performance depends heavily on the number of blocks processed per operation. Processing a
single block results in the minimum engine performance; in this case, the configuration overhead is the
most significant (assuming the engine is fully reconfigured for each operation). Therefore, processing
multiple blocks per operation results in a significantly higher performance.
single block results in the minimum engine performance; in this case, the configuration overhead is the
most significant (assuming the engine is fully reconfigured for each operation). Therefore, processing
multiple blocks per operation results in a significantly higher performance.
10.1.6 Programming Guidelines
This section describes the low-level programming sequences for configuring and using the AES module
for the supported-use cases.
for the supported-use cases.
10.1.6.1 One Time Initialization After a Reset
The purpose of the initialization is to set the AES module into the initial mode common to all used
operations. The following initialization steps should be performed after a hardware reset:
operations. The following initialization steps should be performed after a hardware reset:
•
Read out and check that the AES module version and configuration matches the expected hardware
configuration.
configuration.
•
Program the DMAC run-time parameters (DMABUSCFG register) with the desired values common for
all DMA operations.
all DMA operations.
•
Initialize the desired interrupt type (level), and enable the interrupt output signal RESULT_AVAIL in the
master control module.
master control module.
10.1.6.2 DMAC and Master Control
This section contains general guidelines on how to program the DMAC to perform a specific operation.
10.1.6.2.1 Regular Use
The following registers must be programmed to configure the DMA channels:
•
Clear any outstanding interrupts and error flags if possible.
•
The master control module algorithm-selection register should be programmed to allow a DMA
operation on the required internal module, which enables the DMA/AHB Master clock, and keeps it
enabled until the clock is disabled by the host
operation on the required internal module, which enables the DMA/AHB Master clock, and keeps it
enabled until the clock is disabled by the host
•
Channel control registers with channel bits enabled.
•
Channel external address registers.
•
Channel DMA length registers. Writing this register starts the DMA operation on the corresponding
channel.
channel.
•
Completion of the operation is indicated by the result available interrupt output or the corresponding
status register. Clear the interrupt after handling it.
status register. Clear the interrupt after handling it.
•
Master control module algorithm selection register must be cleared to zero to switch off the DMA/AHB
811
SWCU117A – February 2015 – Revised March 2015
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