Texas Instruments CC2650DK 사용자 설명서
AES Cryptoprocessor Overview
10.1.6.3.3.4 Programming Sequence With DMA Data
The following software example in pseudo-code describes the actions that are typically executed by the
host software to encrypt (using a basic AES mode) a message, stored in external memory and place an
encrypted result into a preallocated area in the external memory.
host software to encrypt (using a basic AES mode) a message, stored in external memory and place an
encrypted result into a preallocated area in the external memory.
// configure the master control module
write ALGSEL 0x0000_0002 // enable the DMA path to the AES engine
write IRQCLR 0x0000_0001 // clear any outstanding events
// configure the key store to provide pre-loaded AES key
write KEYREADAREA 0x0000_0000 // load the key from ram area 0 (NOTE: The key
// must be pre-loaded to this area)
wait KEYREADAREA[31]==’0’ // wait until the key is loaded to the AES module
check IRQSTAT[29] = ‘0’ // check that the key is loaded without errors
// Write the IV for non-ECB modes
// The IV must be written with the same conventions as the data (refer to 6.4.1 in IP docs)
if ((not ECB mode) and (not IV reuse)) then:
// write the initialization vector when a new IV is required
write AESIV_0
...
write AESIV_3
endif
// configure AES engine
write AESCTL = 0b0010_0000_0000_0000_
0000_0000_0010_1100 // program AES-CBC-128 encryption and save IV
write AESDATALEN0 // write length of the message (lo)
write AESDATALEN1 // write length of the message (hi)
write DMACH0CTL 0x0000_00001 // enable DMA channel 0// configure DMAC
write DMACH0EXTADDR <address> // base address of the input data in ext. memory
write DMACH0LEN <length> // input data length in bytes, equal to the message
// length (may be non-block size aligned)
write DMACH1CTL 0x0000_00001 // enable DMA channel 1
write DMACH1EXTADDR <address> // base address of the output data buffer
write DMACH1LEN <length> // output data length in bytes, equal to the result
// data length (may be non-block size aligned)
// wait for completion
wait IRQSTAT[0]==’1’ // wait for operation completed
check IRQSTAT[31] == ‘0’ // check for absence of errors
write AESALGSEL 0x0000_0000 // disable master control/DMA clock
if (not ECB mode) then: // only if the IV needs to be re-used/read
wait AESCTL[30]==’1’ // wait for SAVED_CONTEXT_RDY bit [30]
read AESIV_0
...
read AESIV_3 // this read clears the SAVED_CONTEXT_RDY flag
endif
// end of algorithm
816
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated