Texas Instruments CC2650DK 사용자 설명서
Cryptography Registers
Table 10-29. AESCTL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
15
CBC_MAC
R/W
X
MAC mode enable. The DIR bit must be set to 1 for this mode.
Selecting this mode requires writing the AESDATALEN1.LEN_MSW
and AESDATALEN0.LEN_LSW registers after all other registers.
Selecting this mode requires writing the AESDATALEN1.LEN_MSW
and AESDATALEN0.LEN_LSW registers after all other registers.
14-9
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
8-7
CTR_WIDTH
R/W
X
Specifies the counter width for AES-CTR mode
0h = 32_BIT : 32 bits
1h = 64_BIT : 64 bits
2h = 96_BIT : 96 bits
3h = 128_BIT : 128 bits
6
CTR
R/W
X
AES-CTR mode enable This bit must also be set for CCM, when
encryption/decryption is required.
encryption/decryption is required.
5
CBC
R/W
X
CBC mode enable
4-3
KEY_SIZE
R
X
This field specifies the key size. The key size is automatically
configured when a new key is loaded via the key store module. 00 =
N/A - reserved 01 = 128 bits 10 = N/A - reserved 11 = N/A -
reserved For the Crypto peripheral this field is fixed to 128 bits.
configured when a new key is loaded via the key store module. 00 =
N/A - reserved 01 = 128 bits 10 = N/A - reserved 11 = N/A -
reserved For the Crypto peripheral this field is fixed to 128 bits.
2
DIR
R/W
X
Direction. 0 : Decrypt operation is performed. 1 : Encrypt operation is
performed. This bit must be written with a 1 when CBC-MAC is
selected.
performed. This bit must be written with a 1 when CBC-MAC is
selected.
1
INPUT_RDY
R/W
X
If read as 1, this status bit indicates that the 16-byte AES input buffer
is empty. The Host is permitted to write the next block of data.
Writing a 0 clears the bit to zero and indicates that the AES engine
can use the provided input data block. Writing a 1 to this bit will be
ignored. Note: For DMA operations, this bit is automatically
controlled by the Crypto peripheral. After reset, this bit is 0. After
writing a context (note 1), this bit will become 1. For typical use, this
bit does NOT need to be written, but is used for status reading only.
In this case, this status bit is automatically maintained by the Crypto
peripheral.
is empty. The Host is permitted to write the next block of data.
Writing a 0 clears the bit to zero and indicates that the AES engine
can use the provided input data block. Writing a 1 to this bit will be
ignored. Note: For DMA operations, this bit is automatically
controlled by the Crypto peripheral. After reset, this bit is 0. After
writing a context (note 1), this bit will become 1. For typical use, this
bit does NOT need to be written, but is used for status reading only.
In this case, this status bit is automatically maintained by the Crypto
peripheral.
0
OUTPUT_RDY
R/W
X
If read as 1, this status bit indicates that an AES output block is
available to be retrieved by the Host. Writing a 0 clears the bit to
zero and indicates that output data is read by the Host. The AES
engine can provide a next output data block. Writing a 1 to this bit
will be ignored. Note: For DMA operations, this bit is automatically
controlled by the Crypto peripheral. For typical use, this bit does
NOT need to be written, but is used for status reading only. In this
case, this status bit is automatically maintained by the Crypto
peripheral.
available to be retrieved by the Host. Writing a 0 clears the bit to
zero and indicates that output data is read by the Host. The AES
engine can provide a next output data block. Writing a 1 to this bit
will be ignored. Note: For DMA operations, this bit is automatically
controlled by the Crypto peripheral. For typical use, this bit does
NOT need to be written, but is used for status reading only. In this
case, this status bit is automatically maintained by the Crypto
peripheral.
845
SWCU117A – February 2015 – Revised March 2015
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