Texas Instruments CC2650DK 사용자 설명서
Cryptography Registers
10.2.1.26 AESDATAIN1 Register (Offset = 564h) [reset = X]
AESDATAIN1 is shown in
and described in
AES Data Input/Output 1
Figure 10-28. AESDATAIN1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DATA
W-X
Table 10-36. AESDATAIN1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
DATA
W
X
Data registers for input block data to the Crypto peripheral. These
bits = AES Input Data[63:32] of [127:0] For normal operations, this
register is not used, since data input and output is transferred from
and to the AES engine via DMA. For a Host write operation, these
registers must be written with the 128-bit input block for the next
AES operation. Writing at a word-aligned offset within this address
range will store the word (4 bytes) of data into the corresponding
position of 4-word deep (16 bytes = 128-bit AES block) data input
buffer. This buffer is used for the next AES operation. If the last data
block is not completely filled with valid data (see notes below), it is
allowed to write only the words with valid data. Next AES operation
is triggered by writing to AESCTL.INPUT_RDY. Note: AES typically
operates on 128 bits block multiple input data. The CTR, GCM and
CCM modes form an exception. The last block of a CTR-mode
message may contain less than 128 bits (refer to [NIST 800-38A]): 0
< n <= 128 bits. For GCM/CCM, the last block of both AAD and
message data may contain less than 128 bits (refer to [NIST 800-
38D]). The Crypto peripheral automatically pads or masks
misaligned ending data blocks with zeroes for GCM, CCM and CBC-
MAC. For CTR mode, the remaining data in an unaligned data block
is ignored.
bits = AES Input Data[63:32] of [127:0] For normal operations, this
register is not used, since data input and output is transferred from
and to the AES engine via DMA. For a Host write operation, these
registers must be written with the 128-bit input block for the next
AES operation. Writing at a word-aligned offset within this address
range will store the word (4 bytes) of data into the corresponding
position of 4-word deep (16 bytes = 128-bit AES block) data input
buffer. This buffer is used for the next AES operation. If the last data
block is not completely filled with valid data (see notes below), it is
allowed to write only the words with valid data. Next AES operation
is triggered by writing to AESCTL.INPUT_RDY. Note: AES typically
operates on 128 bits block multiple input data. The CTR, GCM and
CCM modes form an exception. The last block of a CTR-mode
message may contain less than 128 bits (refer to [NIST 800-38A]): 0
< n <= 128 bits. For GCM/CCM, the last block of both AAD and
message data may contain less than 128 bits (refer to [NIST 800-
38D]). The Crypto peripheral automatically pads or masks
misaligned ending data blocks with zeroes for GCM, CCM and CBC-
MAC. For CTR mode, the remaining data in an unaligned data block
is ignored.
852
SWCU117A – February 2015 – Revised March 2015
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