Texas Instruments CC2650DK 사용자 설명서
Cryptography Registers
10.2.1.32 ALGSEL Register (Offset = 700h) [reset = X]
ALGSEL is shown in
and described in
Master Algorithm Select This register configures the internal destination of the DMA controller.
Figure 10-34. ALGSEL Register
31
30
29
28
27
26
25
24
TAG
RESERVED
R/W-X
R/W-X
23
22
21
20
19
18
17
16
RESERVED
R/W-X
15
14
13
12
11
10
9
8
RESERVED
R/W-X
7
6
5
4
3
2
1
0
RESERVED
AES
KEY_STORE
R/W-X
R/W-X
R/W-X
Table 10-42. ALGSEL Register Field Descriptions
Bit
Field
Type
Reset
Description
31
TAG
R/W
X
If this bit is cleared to 0, the DMA operation involves only data. If this
bit is set, the DMA operation includes a TAG (Authentication Result /
Digest).
bit is set, the DMA operation includes a TAG (Authentication Result /
Digest).
30-2
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
1
AES
R/W
X
If set to 1, the AES data is loaded via DMA Both Read and Write
maximum transfer size to DMA engine is set to 16 bytes
maximum transfer size to DMA engine is set to 16 bytes
0
KEY_STORE
R/W
X
If set to 1, selects the Key Store to be loaded via DMA. The
maximum transfer size to DMA engine is set to 32 bytes (however
transfers of 16, 24 and 32 bytes are allowed)
maximum transfer size to DMA engine is set to 32 bytes (however
transfers of 16, 24 and 32 bytes are allowed)
858
SWCU117A – February 2015 – Revised March 2015
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