Texas Instruments CC2650DK 사용자 설명서
Cryptography Registers
10.2.1.37 IRQCLR Register (Offset = 788h) [reset = X]
IRQCLR is shown in
and described in
Interrupt Clear
Figure 10-39. IRQCLR Register
31
30
29
28
27
26
25
24
DMA_BUS_ER
KEY_ST_WR_
KEY_ST_RD_E
RESERVED
R
ERR
RR
W-X
W-X
W-X
W-X
23
22
21
20
19
18
17
16
RESERVED
W-X
15
14
13
12
11
10
9
8
RESERVED
W-X
7
6
5
4
3
2
1
0
RESERVED
DMA_IN_DON
RESULT_AVAI
E
L
W-X
W-X
W-X
Table 10-47. IRQCLR Register Field Descriptions
Bit
Field
Type
Reset
Description
31
DMA_BUS_ERR
W
X
If 1 is written to this bit, IRQSTAT.DMA_BUS_ERR is cleared.
30
KEY_ST_WR_ERR
W
X
If 1 is written to this bit, IRQSTAT.KEY_ST_WR_ERR is cleared.
29
KEY_ST_RD_ERR
W
X
If 1 is written to this bit, IRQSTAT.KEY_ST_RD_ERR is cleared.
28-2
RESERVED
W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
1
DMA_IN_DONE
W
X
If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is cleared.
0
RESULT_AVAIL
W
X
If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is cleared.
863
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated