Texas Instruments CC2650DK 사용자 설명서
Cortex-M3 Processor Registers
2.7.1.36 LAR Register (Offset = FB0h) [reset = X]
LAR is shown in
and described in
Lock Access This register is used to prevent write accesses to the Control Registers: TER, TPR and TCR.
Figure 2-39. LAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
LOCK_ACCESS
W-X
Table 2-62. LAR Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
LOCK_ACCESS
W
X
A privileged write of 0xC5ACCE55 enables more write access to
Control Registers TER, TPR and TCR. An invalid write removes
write access.
Control Registers TER, TPR and TCR. An invalid write removes
write access.
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SWCU117A – February 2015 – Revised March 2015
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