Texas Instruments CC2650DK 사용자 설명서
Cortex-M3 Processor Registers
Table 2-65. CTRL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
15-13
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
12
PCSAMPLEENA
R/W
X
Enables PC Sampling event. A PC sample event is emitted when the
POSTCNT counter triggers it. See CYCTAP and POSTPRESET for
details. Enabling this bit overrides CYCEVTENA. 0: PC Sampling
event disabled. 1: Sampling event enabled.
POSTCNT counter triggers it. See CYCTAP and POSTPRESET for
details. Enabling this bit overrides CYCEVTENA. 0: PC Sampling
event disabled. 1: Sampling event enabled.
11-10
SYNCTAP
R/W
X
Selects a synchronization packet rate. CYCCNTENA and
CPU_ITM:TCR.SYNCENA must also be enabled for this feature.
Synchronization packets (if enabled) are generated on tap transitions
(0 to1 or 1 to 0).
CPU_ITM:TCR.SYNCENA must also be enabled for this feature.
Synchronization packets (if enabled) are generated on tap transitions
(0 to1 or 1 to 0).
0h = Disabled. No synchronization packets
1h = Tap at bit 24 of CYCCNT
2h = Tap at bit 26 of CYCCNT
3h = Tap at bit 28 of CYCCNT
9
CYCTAP
R/W
X
Selects a tap on CYCCNT. These are spaced at bits [6] and [10].
When the selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it
emits into the POSTCNT, post-scalar counter. That counter then
counts down. On a bit change when post-scalar is 0, it triggers an
event for PC sampling or cycle count event (see details in
CYCEVTENA).
When the selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it
emits into the POSTCNT, post-scalar counter. That counter then
counts down. On a bit change when post-scalar is 0, it triggers an
event for PC sampling or cycle count event (see details in
CYCEVTENA).
0h = Selects bit [6] to tap
1h = Selects bit [10] to tap
8-5
POSTCNT
R/W
X
Post-scalar counter for CYCTAP. When the selected tapped bit
changes from 0 to 1 or 1 to 0, the post scalar counter is down-
counted when not 0. If 0, it triggers an event for PCSAMPLEENA or
CYCEVTENA use. It also reloads with the value from
POSTPRESET.
changes from 0 to 1 or 1 to 0, the post scalar counter is down-
counted when not 0. If 0, it triggers an event for PCSAMPLEENA or
CYCEVTENA use. It also reloads with the value from
POSTPRESET.
4-1
POSTPRESET
R/W
X
Reload value for post-scalar counter POSTCNT. When 0, events are
triggered on each tap change (a power of 2). If this field has a non-0
value, it forms a count-down value, to be reloaded into POSTCNT
each time it reaches 0. For example, a value 1 in this register means
an event is formed every other tap change.
triggered on each tap change (a power of 2). If this field has a non-0
value, it forms a count-down value, to be reloaded into POSTCNT
each time it reaches 0. For example, a value 1 in this register means
an event is formed every other tap change.
0
CYCCNTENA
R/W
X
Enable CYCCNT, allowing it to increment and generate
synchronization and count events. If NOCYCCNT = 1, this bit reads
zero and ignore writes.
synchronization and count events. If NOCYCCNT = 1, this bit reads
zero and ignore writes.
94
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated