Texas Instruments TPS712xx Evaluation Module TPS712XXEVM-050 TPS712XXEVM-050 데이터 시트
제품 코드
TPS712XXEVM-050
www.ti.com
4
Board Layout
4.1
Layout
Texas Instruments
TPS712xxEVM−050
TPS713xxEVM−050
HPA050 Rev A
TPS712xxEVM−050
TPS713xxEVM−050
HPA050 Rev A
J1
J2
ON EN1 OFF
ON EN2 OFF
GND
GND
GND
GND
VOUT1
VOUT2
GND
VOUT1
VOUT2
R2
R6
J3
J4
J12
J13
J10
J11
J6
J5
RESET
ON EN1 OFF
ON EN2 OFF
GND RESET
VIN
GND
C
1
R
1
R
3
R
5
R
4
C
4
2005
C6
C5
U1
1
C3
C2
JP1
JP2
J7
J8
VIN
U2
1
C8
C7
C11
R
9
R
8
C
9
C10
R10
R7
GND
JP3
JP4
J14
J9
Board Layout
This section provides the TPS712xxEVM-050 board layout and illustrations.
Note:
Board layouts are not to scale. These figures are intended to show how the board is laid
out; they are not intended to be used for manufacturing TPS712xxEVM PCBs.
Board layouts are not to scale. These figures are intended to show how the board is laid
out; they are not intended to be used for manufacturing TPS712xxEVM PCBs.
Board layout is critical for best PSRR and output accuracy.
,
, and
show the
board layout for the TPS712xxEVM-050 PCB. Careful attention has been given to the placement of input,
output, and noise reduction capacitors. For best accuracy with adjustable devices, the feedback point
should be connected at the load.
output, and noise reduction capacitors. For best accuracy with adjustable devices, the feedback point
should be connected at the load.
Figure 1. Assembly Layer
TPS712xxEVM User's Guide
SBVU010 – February 2005
3