Texas Instruments Evaluation Module for TPS54319 Step-Down SWIFT DC/DC Converter TPS54319EVM-626 TPS54319EVM-626 데이터 시트
제품 코드
TPS54319EVM-626
Vin = 5 V / div
Vout = 2 V / div
EN = 2 V / div
PWRGD = 5 V / div
Time = 5 msec / div
www.ti.com
Board Layout
2.9.2
Power Up Relative to EN
The start-up waveform shown in
shows start-up is relative to EN rising. The input voltage is
initially applied and allowed to reach 5V while EN is held low by installing a jumper across JP1. When the
jumper is removed, the device is enabled and the start-up sequence begins. The output ramps up at the
externally set rate toward the set value of 1.8 V. The input voltage for this plot is 5 V with a 2
jumper is removed, the device is enabled and the start-up sequence begins. The output ramps up at the
externally set rate toward the set value of 1.8 V. The input voltage for this plot is 5 V with a 2
Ω
load.
Figure 10. TPS54319EVM-626 Start-Up Relative to EN
3
Board Layout
This section provides a description of the TPS54319EVM-626, board layout, and layer illustrations.
3.1
Layout
The board layout for the TPS54319EVM-626 is shown in
through
. The top-side layer
of the EVM is laid out in a manner typical of a user application. The top and bottom layers are 2-oz
copper.
copper.
The top layer contains the main power traces for V
IN
, V
OUT
, and VPHASE. The top layer also has
connections for the remaining pins of the TPS54319, and a large area filled with ground. The two internal
layers and bottom layer contain ground planes. The top and bottom and internal ground traces are
connected with multiple vias placed around the board including four vias directly under the TPS54319
device to provide a thermal path from the top-side ground area to the bottom-side ground plane.
layers and bottom layer contain ground planes. The top and bottom and internal ground traces are
connected with multiple vias placed around the board including four vias directly under the TPS54319
device to provide a thermal path from the top-side ground area to the bottom-side ground plane.
The input decoupling capacitors (C2 and C3) and bootstrap capacitor (C6) are all located as close to the
IC as possible. In addition, the voltage set-point resistor divider components are also kept close to the IC.
The voltage divider network ties to the output voltage at the point of regulation, the copper V
IC as possible. In addition, the voltage set-point resistor divider components are also kept close to the IC.
The voltage divider network ties to the output voltage at the point of regulation, the copper V
OUT
trace at
the output connector (J2). For the TPS54319, an additional input bulk capacitor may be required (C1),
depending on the EVM connection to the input supply.
depending on the EVM connection to the input supply.
9
SLVU377 – May 2010
TPS54319EVM-626 3-A, SWIFT™ Regulator Evaluation Module
Copyright © 2010, Texas Instruments Incorporated