Texas Instruments Evaluation Module for TPS5432 3A Synchronous Step-Down Converter TPS5432EVM-116 TPS5432EVM-116 데이터 시트
제품 코드
TPS5432EVM-116
V
= 1 V/div
OUT
Time = 2 ms/div
EN = 2 V/div
V
= 5 V/div
IN
SS = 2 V/div
Board Layout
2.10.2
Shut Down Relative to EN
The shut down waveform shown in
shows shut down relative to EN falling. EN is pulled low by
shorting TP4 to GND and the device is disabled. The input voltage for this plot is 5 V with a 1
Ω
load.
Figure 12. TPS5432EVM-116 Shut Down Relative to EN
3
Board Layout
This section provides a description of the TPS5432EVM-116, board layout, and layer illustrations.
3.1
Layout
The board layout for the TPS5432EVM-116 is shown in
through
. The top-side layer of
the EVM is laid out in a manner typical of a user application. The top and bottom layers are 2-oz copper.
The top layer contains the main power traces for V
IN
, V
OUT
, and VPHASE. The top layer also has
connections for the remaining pins of the TPS5432, and a large area filled with ground. The bottom layer
contains a ground plane. The top and bottom and internal ground traces are connected with multiple vias
placed around the board including four vias directly under the TPS5432 device to provide a thermal path
from the top-side ground area to the bottom-side ground plane.
contains a ground plane. The top and bottom and internal ground traces are connected with multiple vias
placed around the board including four vias directly under the TPS5432 device to provide a thermal path
from the top-side ground area to the bottom-side ground plane.
The input decoupling capacitors (C1 and C2) and bootstrap capacitor (C6) are all located as close to the
IC as possible. In addition, the voltage set-point resistor divider components are also kept close to the IC.
The voltage divider network ties to the output voltage at the point of regulation, the copper V
IC as possible. In addition, the voltage set-point resistor divider components are also kept close to the IC.
The voltage divider network ties to the output voltage at the point of regulation, the copper V
OUT
trace at
the output connector (J2). For the TPS5432, an additional input bulk capacitor may be required,
depending on the EVM connection to the input supply. The sensitive analog returns for C3, C4, C5 and R7
are connected to a dedicated ground area on the top side. This ground area fill is connected to the power
ground area fill by a wide trace routed close to the IC. Connecting the two ground areas at a single point
eliminates circulating currents.
depending on the EVM connection to the input supply. The sensitive analog returns for C3, C4, C5 and R7
are connected to a dedicated ground area on the top side. This ground area fill is connected to the power
ground area fill by a wide trace routed close to the IC. Connecting the two ground areas at a single point
eliminates circulating currents.
10
TPS5432EVM-116 3-A, SWIFT™ Regulator Evaluation Module
SLVU674 – March 2012
Copyright © 2012, Texas Instruments Incorporated