Texas Instruments Evaluation Module for TPS5432 3A Synchronous Step-Down Converter TPS5432EVM-116 TPS5432EVM-116 데이터 시트
제품 코드
TPS5432EVM-116
×
-
REF
OUT
REF
R6 V
R7 =
V
V
Test Setup and Results
1.3
Modifications
These evaluation modules are designed to provide access to the features of the TPS5432. Some
modifications can be made to this module.
modifications can be made to this module.
1.3.1
Output Voltage Set Point
The voltage divider of R6 and R7 is used to set the output voltage of the EVM. The 49.9
Ω
resistor R5 is
provided as an aid to check the loop response of the circuit. To change the output voltage of the EVM, it is
necessary to change the value of resistor R7 while leaving R6 set at 10.0 k
necessary to change the value of resistor R7 while leaving R6 set at 10.0 k
Ω
. Changing the value of R7
can change the output voltage above the reference voltage, 0.808 V. The value of R7 for a specific output
voltage can be calculated using
voltage can be calculated using
.
(1)
lists the R7 values for some common output voltages. Note that V
IN
must be in a range so that the
minimum on-time is greater than 60 ns, and the maximum duty cycle is less than 95.8%. Higher duty
cycles are possible, but may result in uneven switching behavior. The values given in
cycles are possible, but may result in uneven switching behavior. The values given in
are
standard values, not the exact value calculated using
.
Table 3. Common Output Voltages
Output Voltage
R7 Value
(V)
(k
Ω
)
1.2
20.5
1.5
11.8
1.8
8.06
2.5
4.75
3.3
3.24
Be aware that changing the output voltage can affect the loop response. It may be necessary to modify
the compensation components. See the data sheet (
the compensation components. See the data sheet (
) for details.
1.3.2
Slow-Start and UVLO
The slow-start time and UVLO voltage may also be adjusted. C3 sets the slow-start time and the resistor
divider of R1 and R2 sets the UVLO start and stop voltages. To use the external UVLO function, ensure
that shunts are installed across JP1 and JP2. See the TPS5432 (
divider of R1 and R2 sets the UVLO start and stop voltages. To use the external UVLO function, ensure
that shunts are installed across JP1 and JP2. See the TPS5432 (
) data sheet for details on
adjusting these parameters.
2
Test Setup and Results
This section describes how to properly connect, set up, and use the TPS5432EVM-116 evaluation
module. The section also includes test results typical for the evaluation module and covers efficiency,
output voltage regulation, load transients, loop response, output ripple, input ripple, and start-up.
module. The section also includes test results typical for the evaluation module and covers efficiency,
output voltage regulation, load transients, loop response, output ripple, input ripple, and start-up.
2.1
Input/Output Connections
The TPS5432EVM-116 is provided with input/output connectors and test points as shown in
. A
power supply capable of supplying 1.5 A must be connected to J1 through a pair of 20 AWG wires. The
load must be connected to J2 through a pair of 20 AWG wires. The minimum load current capability must
be 3 A. Wire lengths must be minimized to reduce losses in the wires. Test-point TP1 provides a place to
monitor the V
load must be connected to J2 through a pair of 20 AWG wires. The minimum load current capability must
be 3 A. Wire lengths must be minimized to reduce losses in the wires. Test-point TP1 provides a place to
monitor the V
IN
input voltages with TP2 providing a convenient ground reference. TP12 is used to monitor
the output voltage with TP13 as the ground reference.
3
SLVU674 – March 2012
TPS5432EVM-116 3-A, SWIFT™ Regulator Evaluation Module
Copyright © 2012, Texas Instruments Incorporated