Texas Instruments TPS7A8300 Low-Dropout Voltage Regulator Evaluation Module TPS7A8300EVM-209 TPS7A8300EVM-209 데이터 시트
제품 코드
TPS7A8300EVM-209
Operation
2.2
Soldering Guidelines
Any solder re-work to modify the EVM for the purpose of repair or other application reasons must be
performed using a hot-air system to avoid damaging the integrated circuit (IC).
performed using a hot-air system to avoid damaging the integrated circuit (IC).
2.3
Equipment Interconnect
•
Set the input and bias power supply to 6.5 V(max). Turn the power supply off. Connect the positive
voltage lead from input power supply to VIN, at the J1 connector of the EVM. Connect the ground lead
from the input power supply to GND at the J2 connector of the EVM.
voltage lead from input power supply to VIN, at the J1 connector of the EVM. Connect the ground lead
from the input power supply to GND at the J2 connector of the EVM.
•
Connect a 0- to 2-A load between OUT and GND. The connector used depends on the desired output
current.
current.
•
Disable the output by floating JP1.
3
Operation
•
Turn on the power supplies.
•
Enable the output by jumping JP1, the EN pin, to VIN or VBIAS.
•
Vary the respective load and input voltage as necessary for test purposes.
4
Thermal Guidelines and Layout Recommendations
Thermal management is a key component of design of any power converter and is especially important
when the power dissipation in the LDO is high. Use the following formulas to approximate the maximum
power dissipation for the particular ambient temperature:
when the power dissipation in the LDO is high. Use the following formulas to approximate the maximum
power dissipation for the particular ambient temperature:
T
J
= T
A
+ P
D
x
θ
JA
(1)
P
D
= (V
IN
- V
OUT1
) × I
OUT1
+ (V
IN
- V
OUT2
) × I
OUT2
(2)
Where T
J
is the junction temperature, T
A
is the ambient temperature, P
D
is the power dissipation in the
device (Watts), and
θ
JA
is the thermal resistance from junction to ambient. All temperatures are in degrees
Celsius. The maximum operating junction temperature, T
J,
must not be allowed to exceed 125°C. The
layout design must be copper trace and plane areas smartly, as thermal sinks, in order not to allow T
J
to
exceed the absolute maximum rating under all temperature conditions and voltage conditions across the
part.
part.
repeats information from the Dissipation Ratings Table of the TLV7163318 series data sheet for
comparison with the thermal resistance,
θ
JA
, for High-K JEDEC standard boards. The maximum input
voltage can be calculated for full loads at different ambient temperatures. The input voltage must be less
than these values in order to maintain a safe junction temperature.
than these values in order to maintain a safe junction temperature.
Table 1. Thermal Resistance,
θ
JA
, and Maximum Power Dissipation
IC
Board
Package
θ
JA
Max Dissipation (T
A
=
Max Dissipation @2A
25°C)
(T
A
= 70°C)
TPS7A8300
High-K
RGW
35.7°C/W
2.80 W
1.54 W
3
SLVU919 – June 2013
TPS7A8300EVM-209 Evaluation Module
Copyright © 2013, Texas Instruments Incorporated