Texas Instruments SRC4382 Evaluation Module (EVM) and USB motherboard SRC4382EVM-PDK SRC4382EVM-PDK 데이터 시트
제품 코드
SRC4382EVM-PDK
www.ti.com
SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007
Table 3. Control and Status Register Map (Register Page 0)
ADDRESS
D7
(Hex)
(MSB)
D6
D5
D4
D3
D2
D1
D0
REGISTER GROUP
01
RESET
0
PDALL
PDPA
PDPB
PDTX
PDRX
PDSRC
Power-Down and Reset
02
0
0
0
0
0
TX
RX
SRC
Global Interrupt Status
03
0
AMUTE
AOUTS1
AOUTS0
AM/S
AFMT2
AFMT1
AFMT0
Port A Control
04
0
0
0
0
ACLK1
ACLK0
ADIV1
ADIV0
Port A Control
05
0
BMUTE
BOUTS1
BOUTS0
BM/S
BFMT2
BFMT1
BFMT0
Port B Control
06
0
0
0
0
BCLK1
BCLK0
BDIV1
BDIV0
Port B Control
07
TXCLK
TXDIV1
TXDIV0
TXIS1
TXIS0
BLSM
VALID
BSSL
Transmitter Control
08
BYPMUX1
BYPMUX0
AESMUX
LDMUX
TXBTD
AESOFF
TXMUTE
TXOFF
Transmitter Control
09
0
0
0
0
0
VALSEL
TXCUS1
TXCUS0
Transmitter Control
0A
0
0
RATIO
READY
0
0
TSLIP
TBTI
SRC and DIT Status
0B
0
0
MRATIO
MREADY
0
0
MTSLIP
MTBTI
SRC and DIT Interrupt Mask
0C
RATIOM1
RATIOM0
READYM1
READYM0
TSLIPM1
TSLIPM0
TBTIM1
TBTIM0
SRC and DIT Interrupt Mode
0D
0
0
0
RXBTD
RXCLK
0
RXMUX1
RXMUX
Receiver Control
0E
0
0
0
LOL
RXAMLL
RXCKOD1
RXCKOD0
RXCKOE
Receiver Control
0F
P3
P2
P1
P0
J5
J4
J3
J2
Receiver PLL Configuration
10
J1
J0
D13
D12
D11
D10
D9
D8
Receiver PLL Configuration
11
D7
D6
D5
D4
D3
D2
D1
D0
Receiver PLL Configuration
12
0
0
0
0
0
0
DTS CD/LD
IEC61937
Non-PCM Audio Detection
13
0
0
0
0
0
0
RXCKR1
RXCKR0
Receiver Status
14
CSCRC
PARITY
VBIT
BPERR
QCHG
UNLOCK
QCRC
RBTI
Receiver Status
15
0
0
0
0
0
0
0
OSLIP
Receiver Status
16
MCSCRC
MPARITY
MVBIT
MBPERR
MQCHG
MUNLOCK
MQCRC
MRBTI
Receiver Interrupt Mask
17
0
0
0
0
0
0
0
MOSLIP
Receiver Interrupt Mask
18
QCHGM1
QCHGM0
UNLOCKM1
UNLOCKM0
QCRCM1
QCRCM0
RBTIM1
RBTIM0
Receiver Interrupt Mode
19
CSCRCM1
CSCRCM0
PARITYM1
PARITYM0
VBITM1
VBITM0
BPERRM1
BPERRM0
Receiver Interrupt Mode
1A
0
0
0
0
0
0
OSLIPM1
OSLIPM0
Receiver Interrupt Mode
1B
0
0
0
0
GPO13
GPO12
GPO11
GPO10
General-Purpose Out (GPO1)
1C
0
0
0
0
GPO23
GPO22
GPO21
GPO20
General-Purpose Out (GPO2)
1D
0
0
0
0
GPO33
GPO32
GPO31
GPO30
General-Purpose Out (GPO3)
1E
0
0
0
0
GPO43
GPO42
GPO41
GPO40
General-Purpose Out (GPO4)
1F
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Audio CD Q-Channel Sub-Code
20
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Audio CD Q-Channel Sub-Code
21
Q16
Q17
Q18
Q19
Q20
Q21
Q22
Q23
Audio CD Q-Channel Sub-Code
22
Q24
Q25
Q26
Q27
Q28
Q29
Q30
Q31
Audio CD Q-Channel Sub-Code
23
Q32
Q33
Q34
Q35
Q36
Q37
Q38
Q39
Audio CD Q-Channel Sub-Code
24
Q40
Q41
Q42
Q43
Q44
Q45
Q46
Q47
Audio CD Q-Channel Sub-Code
25
Q48
Q49
Q50
Q51
Q52
Q53
Q54
Q55
Audio CD Q-Channel Sub-Code
26
Q56
Q57
Q58
Q59
Q60
Q61
Q62
Q63
Audio CD Q-Channel Sub-Code
27
Q64
Q65
Q66
Q67
Q68
Q69
Q70
Q71
Audio CD Q-Channel Sub-Code
28
Q72
Q73
Q74
Q75
Q76
Q77
Q78
Q79
Audio CD Q-Channel Sub-Code
29
PC15
PC14
PC13
PC12
PC11
PC10
PC09
PC08
PC Burst Preamble, High Byte
2A
PC07
PC06
PC05
PC04
PC03
PC02
PC01
PC00
PC Burst Preamble, Low Byte
2B
PD15
PD14
PD13
PD12
PD11
PD10
PD09
PD08
PD Burst Preamble, High Byte
2C
PD07
PD06
PD05
PD04
PD03
PD02
PD01
PD00
PD Burst Preamble, Low Byte
2D
0
TRACK
0
MUTE
SRCCLK1
SRCCLK0
SRCIS1
SRCIS0
SRC Control
2E
0
0
AUTODEM
DEM1
DEM0
DDN
IGRP1
IGRP0
SRC Control
2F
OWL1
OWL0
0
0
0
0
0
0
SRC Control
30
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
SRC Control
31
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
SRC Control
32
SRI4
SRI3
SRI2
SRI1
SRI0
SRF10
SRF9
SRF8
SRC Input: Output Ratio
33
SRF7
SRF6
SRF5
SRF4
SRF3
SRF2
SRF1
SRF0
SRC Input: Output Ratio
7F
0
0
0
0
0
0
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