Texas Instruments SRC4382 Evaluation Module (EVM) and USB motherboard SRC4382EVM-PDK SRC4382EVM-PDK 데이터 시트
제품 코드
SRC4382EVM-PDK
www.ti.com
ELECTRICAL CHARACTERISTICS: I
2
C Standard and Fast Modes
SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007
All specifications are at T
A
= +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
SRC4382
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
HOST INTERFACE: I
2
C Standard Mode
(1)
SCL Clock Frequency, f
SCL
0
100
kHz
Hold Time Repeated START Condition, t
HDSTA
4
μ
s
Low Period of SCL Clock, t
LOW
4.7
μ
s
High Period of SCL Clock, t
HIGH
4
μ
s
Setup Time Repeated START Condition, t
SUSTA
4.7
μ
s
Data Hold Time, t
HDDAT
0
(2)
3.45
(3)
μ
s
Data Setup Time, t
SUDAT
250
ns
Rise Time for Both SDA and SDL, t
R
1000
ns
Fall Time for Both SDA and SDL, t
F
300
ns
Setup Time for STOP Condition, t
SUSTO
4
μ
s
Bus Free Time Between START and STOP, t
BUF
4.7
μ
s
Capacitive Load for Each Bus Line, C
B
400
pF
Noise Margin at Low Level (including hysteresis), V
NL
0.1
נ
VIO
V
Noise Margin at High Level (including hysteresis), V
NH
0.2
נ
VIO
V
HOST INTERFACE: I
2
C Fast Mode
(1)
SCL Clock Frequency, f
SCL
0
400
kHz
Hold Time Repeated START Condition, t
HDSTA
0.6
μ
s
Low Period of SCL Clock, t
LOW
1.3
μ
s
High Period of SCL Clock, t
HIGH
0.6
μ
s
Setup Time Repeated START Condition, t
SUSTA
0.6
μ
s
Data Hold Time, t
HDDAT
0
(2)
0.9
(3)
μ
s
Data Setup Time, t
SUDAT
100
(4)
ns
Rise Time for Both SDA and SDL, t
R
20 + 0.2C
B
(5)
300
ns
Fall Time for Both SDA and SDL, t
F
20 + 0.2C
B
(5)
300
ns
Setup Time for STOP Condition, t
SUSTO
0.6
μ
s
Bus Free Time Between START and STOP, t
BUF
1.3
μ
s
Spike Pulse Width Suppressed by Input Filter, t
SP
0
50
ns
Capacitive Load for Each Bus Line, C
B
400
pF
Noise Margin at Low Level (including hysteresis), V
NL
0.1
נ
VIO
V
Noise Margin at High Level (including hysteresis), V
NH
0.2
נ
VIO
V
(1)
All values referred to the V
IH
minimum and V
IL
maximum levels listed in the Digital I/O Characteristics section of the Electrical
Characteristics: General, SRC, DIR, and DIT table.
(2)
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH
minimum input level) to bridge the
undefined region of the falling edge of SCL.
(3)
The maximum t
HDDAT
has only to be met if the device does not stretch the Low period (t
LOW
) of the SCL signal.
(4)
A Fast mode I
2
C bus device can be used in a Standard mode I
2
C bus system, but the requirement that t
SUDAT
be 250ns minimum must
then be met. For the SRC4382, this is automatically the case, since the device does not stretch the Low period of the SCL signal.
(5)
C
B
is defined as the total capacitance of one bus line in picofarads (pF). If mixed with High-Speed mode devices, faster fall times are
allowed.
Copyright © 2006–2007, Texas Instruments Incorporated
7
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