Texas Instruments 0A Evaluation Module Featuring the TPS51117 Synchronous Buck Controller with D-CAP Mode TPS51117EVM TPS51117EVM 데이터 시트
제품 코드
TPS51117EVM
Control
Logic
and
Driver
R1
R2
+
VFB
-
DRVL
I
L
Voltage Divider
PWM
VIN
Lx
DRVH
Io
Vc
Co
ESR
RL
Ic
Switching Modulator
0.75V
+
Output Capacitor
ƒ
o
+
1
2
p
ESR
Co
v
ƒ
sw
4
R1
+
ǒ
V
OUT
*
0.75
Ǔ
0.75
R2
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SLVS631B – DECEMBER 2005 – REVISED SEPTEMBER 2009
APPLICATION INFORMATION
LOOP COMPENSATION AND EXTERNAL PARTS SELECTION
D-CAP™ Mode Operation
A buck converter system using D-CAP™ Mode can be simplified as shown in
Figure 23. Simplified Diagram of the Modulator
The VFB voltage is compared with the internal reference voltage after the divider resistors. The PWM comparator
determines the timing to turn on the top MOSFET. The gain and speed of the comparator is high enough to keep
the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The DC output
voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage increases.
determines the timing to turn on the top MOSFET. The gain and speed of the comparator is high enough to keep
the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The DC output
voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage increases.
For loop stability, the 0 dB frequency, f
0
, defined in the follow equation must be lower than 1/4 of the switching
frequency.
(6)
As f
0
is determined solely by the output capacitor characteristics, loop stability of D-CAP™ Mode is determined
by capacitor chemistry. For example, specialty polymer capacitors (SP-CAP) have Co in the order of several 100
μ
F and ESR in range of 10 m
Ω
. These values make f
0
in the order of 100 kHz or less and the loop is stable.
However, ceramic capacitors have f
0
at more than 700 kHz, which is not suitable for this operational mode.
Although D-CAP™ Mode provides many advantages such as ease-of-use, minimum external component
configuration, and extremely short response time, due to not employing an error amplifier in the loop, a sufficient
feedback signal needs to be provided by an external circuit to reduce the jitter level. The required signal level is
approximately 15 mV at the comparing point. This generates V
configuration, and extremely short response time, due to not employing an error amplifier in the loop, a sufficient
feedback signal needs to be provided by an external circuit to reduce the jitter level. The required signal level is
approximately 15 mV at the comparing point. This generates V
ripple
= (V
OUT
/0.75) × 15 mV at the output node.
The output capacitor ESR should meet this requirement.
The external component selection is simple in D-CAP™ Mode:
1. Determine the value of R1 and R2
The recommended R2 value is 10 k
Ω
to 100 k
Ω
. Calculate R1 by
.
(7)
2. Choose R
TON
Copyright © 2005–2009, Texas Instruments Incorporated
17
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